Programmable amplifiers with positive and negative hysteresis

• US 7,453,299 B1
• Filed: 02/26/2008
• Issued: 11/18/2008
• Est. Priority Date: 03/08/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Bui, John H.
• Primary Examiner(s): Wells; Kenneth B.
• Application Number:
  US12/037,921
• Time in Patent Office: 266 Days
• Field of Search: 327/205, 327/206
• US Class Current: 327/205
• CPC Class Codes: H03F 2203/45364 the AAC comprising multiple transistors parallel coupled at their gates and sources only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

Programmable dynamic amplifiers with hysteresis are provided. The hysteretic amplifiers have a first input voltage threshold when the output voltage is at a high voltage and a second input voltage threshold when the output voltage is at a low voltage. A multiplexer controls the hysteretic threshold voltages in response to the output signal of the amplifier. The hysteretic amplifiers can be programmed to have positive or negative hysteresis. When the amplifier is programmed with positive hysteresis, the output voltage transitions after the input voltages have both reached a common voltage value. When the amplifier is programmed with negative hysteresis, the output voltage transitions before the input voltages have both reached a common voltage value.

Claims

1. A two stage amplifying system comprising

first and second hysteretic amplifiers coupled to receive first and second differential input voltages;

and

a third hysteretic amplifier having inputs coupled to outputs of the first and the second amplifiers,

wherein the first and the second hysteretic amplifiers generate two positive hysteretic thresholds in response to first and second control signals, and two negative hysteretic thresholds in response to the first and the second control signals,

and the third hysteretic amplifier generates two positive hysteretic thresholds in response to third and fourth control signals, and two negative hysteretic thresholds in response to the third and the fourth control signals.

2. An integrated circuit including an input amplifier comprising:

a first differential amplifier coupled to receive a first differential signal and having a first positive hysteresis or a first negative hysteresis depending on a state of a first control signal;

a second differential amplifier coupled to receive the first differential signal and having the first positive hysteresis or the first negative hysteresis depending on the state of the first control signal; and

a third differential amplifier coupled to receive an output from the first differential amplifier and an output from the second differential amplifier, and having a second positive hysteresis or a second negative hysteresis depending on a state of a second control signal.

3. The integrated circuit of claim 2 wherein the first differential amplifier has the first positive hysteresis when the first control signal is in a first state and the third differential amplifier has the second positive hysteresis when the second control signal is in the first state.

4. The integrated circuit of claim 2 wherein an inverting input of the first differential amplifier is coupled to a non-inverting input of the second differential amplifier and a non-inverting input of the first differential amplifier is coupled to an inverting input of the second differential amplifier.

5. The integrated circuit of claim 2 wherein the first and second differential amplifiers each comprise:

a first transistor and a second transistor having gates coupled to receive the first differential input signal;

a third transistor and a fourth transistor having gates coupled to receive the first differential input signal, the source of the third transistor coupled to a source of the first transistor, a source of the second transistor, and a source of the fourth transistor;

a multiplexing circuit coupled to receive the first control signal and to provide a third control signal and a fourth control signal;

a fifth transistor having a gate coupled to receive the third control signal, a source coupled to a drain of the first transistor, and a drain coupled to a drain of the third transistor; and

a sixth transistor having a gate coupled to receive the fourth control signal, a source coupled to a drain of the second transistor, and a drain coupled to a drain of the fourth transistor.

6. The integrated circuit of claim 5 wherein the first and second differential amplifiers further comprise:

a seventh transistor and an eighth transistor having gates coupled to receive the first differential signal and having sources coupled to the sources of the first and second transistors;

a ninth transistor having a source coupled to a drain of the seventh transistor, a drain coupled to a drain of the fifth transistor, and a gate coupled to receive a fifth control signal; and

a tenth transistor having a source coupled to a drain of the eighth transistor, a drain coupled to a drain of the sixth transistor, and a gate coupled to receive a sixth control signal, the fifth and sixth control signals provided by the multiplexing circuit.

7. The integrated circuit of claim 5 wherein the first and second differential amplifiers further comprise:

a seventh transistor having a gate and a drain coupled to the drain of the fifth transistor; and

an eighth transistor having a gate coupled to the gate of the seventh transistor and a drain coupled to the drain of the sixth transistor.

8. The integrated circuit of claim 5 wherein the first, second, third, and fourth transistors are n-channel transistors.

9. The integrated circuit of claim 5 wherein the first, second, third, and fourth transistors are p-channel transistors.

10. The integrated circuit of claim 2 wherein the third differential amplifier comprises:

a first transistor and a second transistor having gates coupled to receive the first differential input signal;

a third transistor and a fourth transistor having gates coupled to receive the first differential input signal, the source of the third transistor coupled to a source of the first transistor, a source of the second transistor, and a source of the fourth transistor;

a multiplexing circuit coupled to receive the second control signal and to provide a third control signal and a fourth control signal;

a fifth transistor having a gate coupled to receive the third control signal, a source coupled to a drain of the first transistor, and a drain coupled to a drain of the third transistor; and

a sixth transistor having a gate coupled to receive the fourth control signal, a source coupled to a drain of the second transistor, and a drain coupled to a drain of the fourth transistor.

11. An integrated circuit including an input amplifier comprising:

a first differential amplifier coupled to receive a first differential signal and having no hysteresis, a first positive hysteresis, or a first negative hysteresis depending on a state of a first control signal and a state of a second control signal;

a second differential amplifier coupled to receive the first differential signal and having no hysteresis, the first positive hysteresis, or the first negative hysteresis depending on the state of the first control signal and the state of the second control signal;

a third differential amplifier coupled to receive an output from the first differential amplifier and an output from the second differential amplifier, and having no hysteresis, a second positive hysteresis, or a second negative hysteresis depending on a state of a third control signal and a state of a fourth control signal.

12. The integrated circuit of claim 11 wherein the first differential amplifier has no hysteresis when the first control signal is in a first state and the third differential amplifier has no hysteresis when the third control signal is in the first state.

13. The integrated circuit of claim 11 wherein an inverting input of the first differential amplifier is coupled to a non-inverting input of the second differential amplifier and a non-inverting input of the first differential amplifier is coupled to an inverting input of the second differential amplifier.

14. The integrated circuit of claim 11 wherein the first and second differential amplifiers each comprise:

a first transistor and a second transistor having gates coupled to receive the first differential input signal;

a third transistor and a fourth transistor having gates coupled to receive the first differential input signal, the source of the third transistor coupled to a source of the first transistor, a source of the second transistor, and a source of the fourth transistor;

a multiplexing circuit coupled to receive the first and second control signals and to provide a fifth control signal and a sixth control signal;

a fifth transistor having a gate coupled to receive the fifth control signal, a source coupled to a drain of the first transistor, and a drain coupled to a drain of the third transistor; and

a sixth transistor having a gate coupled to receive the sixth control signal, a source coupled to a drain of the second transistor, and a drain coupled to a drain of the fourth transistor.

15. The integrated circuit of claim 14 wherein the first and second differential amplifiers further comprise:

a seventh transistor and an eighth transistor having gates coupled to receive the first differential signal and having sources coupled to the sources of the first and second transistors;

a ninth transistor having a source coupled to a drain of the seventh transistor, a drain coupled to a drain of the fifth transistor, and a gate coupled to receive a seventh control signal; and

a tenth transistor having a source coupled to a drain of the eighth transistor, a drain coupled to a drain of the sixth transistor, and a gate coupled to receive an eighth control signal, the seventh and eighth control signal provided by the multiplexing circuit.

16. The integrated circuit of claim 14 wherein the first and second differential amplifiers further comprise:

a seventh transistor having a gate and a drain coupled to the drain of the fifth transistor; and

an eighth transistor having a gate coupled to the gate of the seventh transistor and a drain coupled to the drain of the sixth transistor.

17. The integrated circuit of claim 14 wherein the first, second, third, and fourth transistors are n-channel transistors.

18. The integrated circuit of claim 14 wherein the first, second, third, and fourth transistors are p-channel transistors.

19. The integrated circuit of claim 11 wherein the third differential amplifier comprises:

a first transistor and a second transistor having gates coupled to receive the first differential input signal;

a third transistor and a fourth transistor having gates coupled to receive the first differential input signal, the source of the third transistor coupled to a source of the first transistor, a source of the second transistor, and a source of the fourth transistor;

a multiplexing circuit coupled to receive the third and fourth control signal and to provide a fifth control signal and a sixth control signal;

a fifth transistor having a gate coupled to receive the fifth control signal, a source coupled to a drain of the first transistor, and a drain coupled to a drain of the third transistor; and

a sixth transistor having a gate coupled to receive the sixth control signal, a source coupled to a drain of the second transistor, and a drain coupled to a drain of the fourth transistor.