Predistortion circuit for a transmit system

• US 7,453,952 B2
• Filed: 07/03/2003
• Issued: 11/18/2008
• Est. Priority Date: 07/03/2003
• Status: Active Grant

• Current Assignee: Zarbana Digital Fund LLC (Intellectual Ventures LLC)
• Original Assignee: Zarbana Digital Fund LLC (Intellectual Ventures LLC)
• Inventors: Saed, Aryan, DeCruyenaere, Jean-Paul Rene
• Primary Examiner(s): Ghayour; Mohammed
• Assistant Examiner(s): Williams; Lawrence B
• Application Number:
  US10/613,355
• Publication Number:
  US 20050002470A1
• Time in Patent Office: 1,965 Days
• Field of Search: 375/296, 375/297, 330/2, 330/10, 330/149, 455/114.3, 455/341
• US Class Current: 375/296
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 2201/3233 Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end

Abstract

Systems and methods related to amplifier systems which use a predistortion subsystem to compensate for expected distortions in the system output signal. A predistortion subsystem receives an input signal and applies a predistortion modification to the input signal. The predistortion modification may be a phase modification, a magnitude modification, or a combination of both. The predistorted signal is then received by an amplifier subsystem. The amplifier subsystem decomposes the predistorted signal into separate components, each having a constant envelope phase modulation, and separately amplifies each component. The phase modulated and amplified components are then recombined to arrive at an amplitude and phase modulated and amplified output signal. The predistortion modification is applied to the input to compensate for distortions introduced in the signal by the amplifier subsystem.

Claims

1. A system for processing an input signal, the system comprising:

a predistortion subsystem adapted to receive said input signal and adapted to produce a predistorted signal by applying a deliberate predistortion to said input signal, wherein said predistortion subsystem is adapted to distort said input signal to compensate for distortions in a system output signal; and

a signal processing subsystem adapted to receive and process said predistorted signal and adapted to produce said system output signal, wherein said signal processing subsystem is adapted to decompose said predistorted signal into at least two components, each of said at least two components being processed separately, said signal processing subsystem adapted to combine said at least two components after processing to produce said system output signal, and wherein said signal processing subsystem comprises

a signal decomposer adapted to decompose said predistorted signal into said at least two components,

at least two signal component processor blocks, each of said at least two signal component processor blocks including a respective amplifier, each of said signal component processor blocks adapted to receive a respective one of said at least two components from said signal decomposer, and each of said signal component processor blocks adapted to separately process said respective one of said at least two components and to produce a respective processed output, and

a combiner adapted to receive said respective processed outputs from each of said at least two signal component processor blocks, said combiner producing said system output signal from said respective processed outputs of said at least two signal component processor blocks;

wherein said predistorted signal is represented as a sequence of magnitude and phase pairs; and

wherein said signal decomposer includes a phasor fragmentation engine to receive said sequence of magnitude and phase pairs, said phasor fragmentation engine adapted to decompose said predistorted signal into said at least two components, each of said at least two components exhibiting a respective magnitude and having a respective varying phase, said respective magnitudes of at least two of said at least two components being substantially equal.

2. The system according to claim 1 wherein said respective amplifier comprises a non-linear amplifier.

3. The system according to claim 1 wherein said system is part of a signal transmission system.

4. The system according to claim 1 wherein at least some of said distortions are due to said combiner.

5. The system according to claim 1 wherein said respective amplifier comprises a switch mode amplifier.

6. The system according to claim 1 wherein said respective amplifier has a low-output impedance.

7. The system according to claim 1 wherein said deliberate predistortion includes magnitude distortions adapted to adjust a magnitude of said input signal.

8. A The system according to claim 1 wherein said deliberate predistortion includes phase distortions adapted to adjust a phase of said input signal.

9. The system according to claim 1 wherein said deliberate predistortion is based on at least one entry in a lookup table.

15. The system according to claim 9 wherein said deliberate predistortion is based on an interpolation of entries in said table.

16. A system according to claim 1

wherein said phasor fragmentation engine is configured to convert said sequence of magnitude and phase pairs into two parallel sequences of phasors representing said at least two components, each of said phasors at a respective phase and substantially equal in magnitude to Vmax/2;

and

wherein Vmax is a maximum amplitude of said predistorted signal over a period of said sequence of magnitude and phase pairs.

17. A system according to claim 16

wherein said phasor fragmentation engine is adapted to determine the respective phases of a particular pair of said phasors derived from a particular one of said sequence of magnitude and phase pairs as θ

−

φ and

θ

+φ

respectively; and

wherein V and θ

are a respective magnitude and a respective phase of said particular one of said sequence of magnitude and phase pairs, and φ

=cos<sup>−

1</sup>(V/Vmax).

18. A system according to claim 1 wherein said respective amplifier comprises a class D amplifier.

10. A method of processing an input signal to produce a system output signal, the method comprising:

receiving said input signal;

predistorting, via applying a deliberate predistortion, said input signal to provide a predistorted signal represented as a sequence of magnitude and phase pairs;

decomposing said predistorted signal into at least two component signals;

separately processing each of said at least two component signals, wherein said processing further includes amplifying each of said at least two component signals; and

combining said at least two component signals to produce said system output signal;

wherein said decomposing comprises receiving said sequence of magnitude and phase pairs and producing therefrom said at least two component signals, each of said at least two component signals exhibiting a respective magnitude and having a respective varying phase, said respective magnitudes of at least two of said at least two component signals being substantially equal; and

wherein said decomposing comprises converting said sequence of magnitude and phase pairs into two parallel sequences of phasors representing said at least two component signals, each of said phasors at a respective phase and substantially equal in magnitude to Vmax/2; and

wherein Vmax is a maximum amplitude of said predistorted signal over a period of said sequence of magnitude and phase pairs.

11. The method according to claim 10 wherein said system output signal is an RF modulated version of said input signal.

12. The method according to claim 10 wherein said processing includes phase modulating at least one of said at least two component signals.

13. The method according to claim 10 wherein said receiving further includes accessing an entry in a lookup table, said deliberate predistortion being based, at least in part, on said entry.

14. The method according to claim 13 wherein said deliberate predistortion is based on an interpolation of entries in said table.

19. A method according to claim 10

wherein said decomposing determines the respective phases of a particular pair of said phasors derived from a particular one of said sequence of magnitude and phase pairs as θ

−

φ and

θ

+φ

respectively; and

wherein V and θ

are a respective magnitude and a respective phase of said particular one of said sequence of magnitude and phase pairs, and φ

=cos<sup>−

1</sup>(V/Vmax).