Switch with transparent and non-transparent ports
DC CAFCFirst Claim
1. A switch with transparent and non-transparent ports comprisinga first transparent port for interfacing to a first device having a first address in a first shared address domaina second transparent port for interfacing to a second device having a second address in the first shared address domaina third port for interfacing to a third device having a third address in a second address domain, wherein the second address domain is isolated from the first address domainlogic for routing data units between the first transparent port, the second transparent port and the third port using at least one of memory-mapped I/O and I/O-mapped I/O.
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Abstract
There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports.
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Citations
17 Claims
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1. A switch with transparent and non-transparent ports comprising
a first transparent port for interfacing to a first device having a first address in a first shared address domain a second transparent port for interfacing to a second device having a second address in the first shared address domain a third port for interfacing to a third device having a third address in a second address domain, wherein the second address domain is isolated from the first address domain logic for routing data units between the first transparent port, the second transparent port and the third port using at least one of memory-mapped I/O and I/O-mapped I/O.
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7. A process for switching data units, the process comprising
providing a switch having transparent and non-transparent ports associating the transparent ports with a shared address domain associating the non-transparent ports with non-shared address domains routing data units between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports using at least one of memory-mapped I/O and IO-mapped I/O.
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11. A PCI Express switch with transparent and non-transparent ports comprising
a first transparent port for interfacing to a first device having a first address in a first shared address domain a second transparent port for interfacing to a second device having a second address in the first shared address domain a third port for interfacing to a third device having a third address in a second address domain, wherein the second address domain is isolated from the first address domain logic for routing data units between the first transparent port, the second transparent port and the third port in accordance with a PCI Express interconnect standard.
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17. A method for switching data units, the method comprising
providing a PCI Express switch having transparent and non-transparent ports associating the transparent ports with a shared address domain associating the non-transparent ports with non-shared address domains routing data units between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports in accordance with a PCI Express interconnect standard.
Specification