Power savings apparatus and method for wireless network devices

• US 7,454,634 B1
• Filed: 03/02/2005
• Issued: 11/18/2008
• Est. Priority Date: 08/28/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Tse, Lawrence, Song, Yonghua, Donovan, Timothy, Chung, Chia-Chun, Tran, Tam, Jamal, Shafiq
• Primary Examiner(s): Du; Thuan N
• Application Number:
  US11/070,481
• Time in Patent Office: 1,357 Days
• Field of Search: 713/322, 713/323
• US Class Current: 713/322
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A wireless network device having active and inactive modes comprises a clock generating module that generates a first clock signal having a first clock rate. A voltage supply module generates a first voltage level and a second voltage level that is less than the first voltage level. A first digital module receives the first clock rate and the first voltage level during the active mode, receives the second voltage level during the inactive mode and does not receive the first clock signal during the inactive mode. A first analog module communicates with the voltage supply module and has reduced current consumption during the inactive mode.

Claims

1. A wireless network device having active and inactive modes, comprising:

a clock generating module that generates a first clock signal having a first clock rate;

a voltage supply module that generates a first voltage level and a second voltage level that is less than said first voltage level;

a first digital module that receives said first clock rate and said first voltage level during said active mode, that receives said second voltage level during said inactive mode and that does not receive said first clock signal during said inactive mode; and

a first analog module that communicates with said voltage supply module and that has reduced current consumption during said inactive mode,

wherein the wireless network device is a wireless network communication device.

2. The wireless device of claim 1 wherein said voltage supply module generates a third voltage level and said first analog module receives said third voltage level during said active mode.

3. The wireless device of claim 1 wherein said first analog module reduces said current consumption during said inactive mode in response to a control signal.

4. The wireless device of claim 1 wherein said first analog module receives said first voltage level during both said active and inactive modes and wherein said first analog module reduces said current consumption during said inactive mode in response to a control signal.

5. The wireless device of claim 1 wherein said clock generating module generates a second clock rate.

6. The wireless device of claim 5 wherein said second clock rate is less than said first clock rate.

7. The wireless device of claim 5 further comprising a second digital module that receives said second clock signal during said inactive mode.

8. The wireless device of claim 7 wherein said second digital module receives said second clock signal during said active mode.

9. The wireless device of claim 7 wherein said second digital module receives said second voltage level during said inactive mode.

10. The wireless device of claim 7 wherein said second digital module includes a power management module that includes a counter.

11. The wireless device of claim 5 wherein said clock generating module includes:

a crystal oscillator that generates a first reference frequency, wherein said first clock rate is based on said first reference frequency; and

a low power oscillator that generates a second reference frequency, wherein said second clock rate is based on said second reference frequency.

12. The wireless device of claim 1 wherein said first digital module includes at least one of a modulator, a baseband processor, a demodulator, a medium access control (MAC) module, and a digital module in a clock data recovery (CDR) module.

13. The wireless device of claim 1 wherein said first analog module includes at least one of an RF transceiver, a crystal oscillator, an analog to digital converter (ADC), a digital to analog converter (DAC), a current bias circuit, a voltage bias circuit, and an analog module in a clock data recovery (CDR) module.

14. The wireless device of claim 1 further comprising a second analog module that receives said second voltage level during said active and inactive modes.

15. The wireless device of claim 14 wherein said second analog module includes a low power oscillator.

16. The wireless device of claim 1 further comprising a power on reset module that prevents a logic reset of said first digital module due to operation at said second voltage level during said inactive mode.

17. A method for operating a wireless network device having active and inactive modes, comprising:

generating a first clock signal having a first clock rate;

generating a first voltage level and a second voltage level that is less than said first voltage level;

receiving said first clock rate and said first voltage level at a first digital module of the wireless network device during said active mode;

receiving said second voltage level during said inactive mode at the first digital module, which does not receive said first clock signal during said inactive mode; and

reducing current consumption of a first analog module of the wireless network device during said inactive mode,

wherein the wireless network device is a wireless network communication device.

18. The method of claim 17 further comprising:

generating a third voltage level; and

receiving said third voltage level said first analog module during said active mode.

19. The method of claim 17 further comprising reducing said current consumption of said first analog module during said inactive mode in response to a control signal.

20. The method of claim 17 further comprising:

receiving said first voltage level at said first analog module during both said active and inactive modes; and

reducing said current consumption at said first analog module during said inactive mode in response to a control signal.

21. The method of claim 17 further comprising generating a second clock rate.

22. The method of claim 21 wherein said second clock rate is less than said first clock rate.

23. The method of claim 21 further comprising:

generating a first reference frequency, wherein said first clock rate is based on said first reference frequency; and

generating a second reference frequency, wherein said second clock rate is based on said second reference frequency.

24. The method of claim 17 wherein said first digital module includes at least one of a modulator, a baseband processor, a demodulator, a medium access control (MAC) module, and a digital module in a clock data recovery (CDR) method.

25. The method of claim 17 wherein said first analog module includes at least one of an RF transceiver, a crystal oscillator, an analog to digital converter (ADC), a digital to analog converter (DAC), a current bias circuit, a voltage bias circuit, and an analog method in a clock data recovery (CDR) method.

26. The method of claim 21 further comprising receiving said second clock signal at a second digital module during said inactive mode.

27. The method of claim 26 further comprising receiving said second clock signal said second digital module during said active mode.

28. The method of claim 26 further comprising receiving said second voltage level at said second digital module during said inactive mode.

29. The method of claim 26 further comprising managing power at said second digital module.

30. The method of claim 17 further comprising receiving said second voltage level at said second analog module during said active and inactive modes.

31. The method of claim 30 wherein said second analog method includes a low power oscillator.

32. The method of claim 17 further comprising preventing a logic reset of said first digital module due to operation at said second voltage level during said inactive mode.