Integrated circuit with low current consumption having a one wire communication interface
First Claim
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1. An integrated circuit, comprising:
- a connection terminal for receiving an electric data carrying signal;
means for delivering a first clock signal comprising clock pulses sent after each falling edge of the electric data carrying signal and sent inside a data sampling window;
means for delivering a second clock signal comprising clock pulses sent only when the electric data carrying signal is at the high level;
data processing means clocked by the second clock signal; and
means for extracting from the electric data carrying signal a voltage that electrically powers the data processing means.
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Abstract
An integrated circuit having a connection terminal for receiving an electric data carrying signal, a circuit for delivering a first clock signal having clock pulses sent after each falling edge of the electric data carrying signal and inside a data sampling window, a circuit for delivering a second clock signal having clock pulses sent only when the electric data carrying signal is at the high level, and a data processing circuit clocked by the second clock signal.
16 Citations
32 Claims
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1. An integrated circuit, comprising:
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a connection terminal for receiving an electric data carrying signal; means for delivering a first clock signal comprising clock pulses sent after each falling edge of the electric data carrying signal and sent inside a data sampling window; means for delivering a second clock signal comprising clock pulses sent only when the electric data carrying signal is at the high level; data processing means clocked by the second clock signal; and means for extracting from the electric data carrying signal a voltage that electrically powers the data processing means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for managing current consumption of an integrated circuit having a connection terminal for receiving an electric data carrying signal, and means for delivering a first clock signal having clock pulses sent after each falling edge of the electric data carrying signal, inside a data sampling window, comprising:
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extracting a voltage from the electric data carrying signal; powering elements of the integrated circuit solely by means of the voltage extracted from the electric data carrying signal; delivering a second clock signal comprising clock pulses sent only when the electric data carrying signal is at the high level; and clocking, by means of the second clock signal, elements of the integrated circuit powered by the voltage extracted from the electric data carrying signal. - View Dependent Claims (11, 12, 13, 14, 15)
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16. An integrated circuit, comprising:
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a data processing circuit adapted to process data received from a data signal; a first circuit coupled to the data processing circuit and configured to generate a first clock signal responsive to a falling edge of the data signal to a first level and only inside a sampling window to synchronize the sending and receiving of data; and a second circuit coupled to the first circuit and configured to generate a second clock signal responsive to the first clock signal to synchronize operations of the data processing circuit, the second clock signal sent only when the data signal is at a second level. - View Dependent Claims (17, 18)
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19. A memory read and write circuit, comprising:
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a one-wire input; a register circuit coupled to the one-wire input; a memory circuit coupled to the register circuit; a protocol control circuit coupled to the register circuit; a first circuit for generating a first clock signal responsive to an edge transition of a data signal received at the one-wire input when the data signal is changing to a first level and only within a sampling window; and a second circuit coupled to the first circuit, the protocol control circuit, and the register circuit, the second circuit configured to generate a second clock signal responsive to the first clock signal to synchronize operations of the protocol control circuit, the register circuit, and the memory circuit, the second clock signal sent only when the data signal is at a second level; wherein the memory read and write circuit is solely powered by power extracted from the data signal. - View Dependent Claims (20, 21)
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22. A method of managing current consumption of an integrated circuit having a data processing circuit for processing data received from a data signal, the method comprising:
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generating a first clock signal responsive to an edge transition of the data signal received on a one-wire input that is changing to a first level and only during a sampling window that follows the data signal edge transition to the first level; generating a second clock signal responsive to first clock signal to synchronize operations of the data processing circuit, the second clock signal sent only when the data signal is at a second first level; and extracting power from the data signal and using only the extracted power for operating the integrated circuit. - View Dependent Claims (23, 24)
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25. An integrated circuit, comprising:
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a connection terminal for receiving an electric data carrying signal; means for delivering a first clock signal comprising clock pulses sent after each falling edge of the electric data carrying signal and sent inside a data sampling window; means for delivering a second clock signal comprising clock pulses sent only when the electric data carrying signal is at the high level; data processing means clocked by the second clock signal; and a terminal for receiving an external clock signal and means for injecting the external clock signal onto a conductive line provided for conveying the first clock signal. - View Dependent Claims (26, 27, 28)
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29. A method for managing current consumption of an integrated circuit having a connection terminal for receiving an electric data carrying signal, and means for delivering a first clock signal having clock pulses sent after each falling edge of the electric data carrying signal, inside a data sampling window, comprising:
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extracting a voltage from the electric data carrying signal; powering elements of the integrated circuit solely by means of the voltage extracted from the electric data carrying signal; delivering a second clock signal comprising clock pulses sent only when the electric data carrying signal is at the high level; clocking, by means of the second clock signal, elements of the integrated circuit powered by the voltage extracted from the electric data carrying signal; and a pulse of the second clock signal is generated by logically combining the first clock signal and the electric data carrying signal; and a pulse of the second clock signal is reset after a time slot determined by a delay circuit. - View Dependent Claims (30, 31, 32)
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Specification