In-system signal analysis using a programmable logic device

• US 7,454,658 B1
• Filed: 02/10/2006
• Issued: 11/18/2008
• Est. Priority Date: 02/10/2006
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Baxter, Michael A.
• Primary Examiner(s): McCarthy; Christopher S
• Assistant Examiner(s): GUYTON, PHILIP A
• Application Number:
  US11/352,033
• Time in Patent Office: 1,012 Days
• Field of Search: 714/30, 326/9, 326/38, 326/41, 375/224, 324/76.38, 341/123
• US Class Current: 714/30
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

Method for in-system signal analysis is described. A programmable logic device is coupled within a signal communications system. A signal processing core is instantiated in programmable logic of the programmable logic device. At least one communication signal is provided to the programmable logic device, where the at least one communication signal has a first frequency. The at least one communication signal is sampled at a second frequency which is less than the first frequency to obtain samples thereof. The samples are converted from analog signals to digital signals. The digital signals are analyzed with at least in part the signal processing core.

Claims

1. A method for in-system signal analysis, comprising:

coupling a programmable logic device within a signal communications system;

instantiating a signal processing core in programmable logic of the programmable logic device;

providing at least one communication signal to the programmable logic device, the at least one communication signal having a first frequency;

sampling the at least one communication signal at a second frequency which is less than the first frequency to obtain samples thereof;

converting the samples from analog signals to digital signals; and

processing the digital signals by at least in part the signal processing core.

2. The method according to claim 1, wherein the signal processing core internal to the programmable logic device is for a communication signal analyzer.

3. The method according to claim 2, wherein the processing of the digital signals is done with both a microprocessor and the signal processing core.

4. The method according to claim 3, wherein the microprocessor is one of an embedded microprocessor in the programmable logic device, an instantiated microprocessor in the programmable logic of the programmable logic device, or an external microprocessor coupled to the programmable logic device.

5. The method according to claim 1, wherein the signal processing core internal to the programmable logic device is for a digital sampling oscilloscope.

6. The method according to claim 5, wherein the processing of the digital signals is done with both a microprocessor and the signal processing core.

7. The method according to claim 6, wherein the microprocessor is one of an embedded microprocessor in the programmable logic device, an instantiated microprocessor in the programmable logic of the programmable logic device, or an external microprocessor coupled to the programmable logic device.

8. The method according to claim 1, wherein the signal processing core internal to the programmable logic device is for a time domain reflectometer.

9. The method according to claim 8, wherein the processing of the digital signals is done with both a microprocessor and the signal processing core.

10. The method according to claim 9, wherein the microprocessor is one of an embedded microprocessor in the programmable logic device, an instantiated microprocessor in the programmable logic of the programmable logic device, or an external microprocessor coupled to the programmable logic device.

11. The method according to claim 1, wherein the processing of the digital signals is done with both a microprocessor and the signal processing core.

12. The method according to claim 11, wherein the signal processing core is configured to provide waveform averaging;

and wherein the microprocessor is coupled to receive at least one Fourier Transform related algorithm for the processing of the digital signals averaged.

13. The method according to claim 11, further comprising:

windowing the digital signals with a digital signal processor internal to the programmable logic device;

wherein the microprocessor is coupled to receive at least one Fourier Transform related algorithm for the processing of the digital signals windowed.

14. A method for in-system analysis of signals, comprising:

providing a programmable logic device in a communications system;

instantiating a signal analyzer core in programmable logic of the programmable logic device;

while operating the programmable logic device in the communications system,

generating within the programmable logic device a first reference signal having a first frequency;

converting the first reference signal into a first differential signal, the first differential signal having an adjusted pulse width;

obtaining a second differential signal having a second frequency, the first frequency being a fraction of the second frequency;

sampling the second differential signal responsive to the pulse width of the first differential signal to provide a signal sample as a first analog signal;

converting the first analog signal to a first digital signal in the programmable logic device; and

analyzing the first digital signal at least in part with the signal analyzer core.

15. The method according to claim 14, further comprising adjusting the pulse width of the first differential signal to obtain another signal sample to provide a second analog signal, the first analog signal and the second analog signal being respectively associated with different communication channels.

16. The method according to claim 15, further comprising:

generating within the programmable device a second reference signal;

providing the second differential signal responsive to the second reference signal;

multiplexing the first analog signal and the second analog signal;

selecting the second analog signal for output from the multiplexing;

converting the second analog signal selected to a second digital signal in the programmable logic device; and

analyzing the second digital signal with the signal analyzer core.

17. The method according to claim 16, further comprising:

Fourier transforming the first digital signal to process data in a frequency domain; and

inverse Fourier transforming the first digital signal after the Fourier transforming to provide a frequency compensation envelope.

18. The method according to claim 17, wherein the analyzing the first digital signal includes processing the first digital signal with a microprocessor having access to at least one Fourier Transform algorithm;

and wherein the Fourier transforming and the inverse Fourier transforming are done with the microprocessor.

19. The method according to claim 17, further comprising instantiating the frequency compensation envelope in the programmable logic of the programmable logic device as a frequency compensator coupled to receive the first digital signal.

20. The method according to claim 14, further comprising windowing the first digital signal with a digital signal processor prior to the analyzing thereof.