Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques

• US 7,454,731 B2
• Filed: 09/22/2006
• Issued: 11/18/2008
• Est. Priority Date: 09/22/2006
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Fallah-Tehrani, Peivand, Oh, Nahmsuk, Kasnavi, Alireza
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Tat; Binh C
• Application Number:
  US11/525,578
• Publication Number:
  US 20080077900A1
• Time in Patent Office: 788 Days
• Field of Search: 716 4- 6
• US Class Current: 716/113
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/3315 using static timing analysis [STA]

Abstract

Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.

Claims

1. A computer-implemented method of designing layouts of integrated circuits, the method comprising:

performing a place and route operation on a netlist of an integrated circuit, to produce a layout for the integrated circuit;

extracting parasitics of the integrated circuit based on the netlist and the layout;

performing static timing analysis on the netlist based on the layout and the parasitics, to estimate timing behavior of the netlist and to identify at least one violation by said timing behavior of a corresponding timing requirement at an endpoint of a path in the netlist;

performing engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said timing behavior, and said violation by;

(a) identifying a plurality of victim nets located in a fanin cone of said endpoint and identifying a group of aggressor nets, wherein each aggressor net is capacitively coupled to one of said victim nets;

(b) forming a set of candidate nets including said group of aggressor nets and said plurality of victim nets;

(c) estimating at least one change in timing behavior of each candidate net required to be made to overcome said violation; and

(d) choosing a subset of candidate nets to be repaired from among said set of candidate nets, based on said change estimated in (c);

generating an ECO constraint on timing behavior of said subset, wherein said ECO constraint is to be satisfied by a ECO repair technique to be used to correct said violation;

automatically selecting said ECO repair technique from among a plurality of ECO repair techniques, based on said ECO constraint; and

repairing said layout by applying said ECO repair technique to generate a modified layout corrected for said violation;

wherein said estimating in (c) comprises computing a change in crosstalk delay in at least said victim net by using values of total resistance and total capacitance of said victim net and an aggressor net, and input capacitance of receiver cells of said victim net and said aggressor net, and resistance of said victim net'"'"'s driver cell and resistance of said aggressor net'"'"'s driver cell.

2. The computer-implemented method of claim 1 wherein said estimating comprises:

computing a change in cell delay in an enlarged version of said victim net'"'"'s driver cell; and

computing a change in net delay in at least said victim net using a simplified representation of said path.

3. The computer-implemented method of claim 1 wherein said computing of change in crosstalk delay comprises:

applying a closed form equation for said aggressor net to obtain a maximum height of a bump arising in said victim net due to crosstalk from said aggressor net;

repeating said applying, to obtain at least one additional maximum height of said bump in said victim net, due to crosstalk from at least one additional aggressor net capacitively coupled to said victim net;

summing up maximum heights of said bump in said victim net obtained by said applyings, to obtain a first total of maximum heights of said bump in said victim net;

repeating said applying with an enlarged version of said victim net'"'"'s driver cell, thereby to obtain a smaller maximum height of said bump for each aggressor net capacitively coupled to a repaired version of said victim net, wherein the repaired version of said victim net comprises the enlarged version of said victim net'"'"'s driver cell;

repeating said summing up to obtain a second total of smaller maximum heights of said bump in said repaired victim net; and

scaling an original height of the bump in said victim net obtained from said static timing analysis, with a ratio of said second total to said first total, to obtain an estimate of a final height of said bump in the repaired version of said victim net.

4. The computer-implemented method of claim 3 further comprising:

scaling said final height of the repaired victim net, with a rail-to-rail transition time for said victim net obtained from said static timing analysis and a rail voltage of said victim net obtained from said static timing analysis, to obtain an estimate of crosstalk delay in the repaired victim net.

5. The computer-implemented method of claim 2 wherein said computing of change in net delay comprises:

representing said victim net as a circuit comprising a resistance R_d of said victim net driver cell in series with total resistance R_n of said victim net, and further in series with total capacitance C_n of said victim net, to obtain said simplified representation; and

applying an Elmore Model to said simplified representation to compute

d_Elmore=(R_d+R_n)·

C_n

where d_Elmore is an indication of delay of said victim net;

repeating said applying with a different resistance R′

_d for an enlarged version of said victim net'"'"'s driver cell to compute

d′

_Elmore=(R′

_d+R_n)·

C_n

where d′

_Elmore is an indication of delay of the enlarged version of said victim net; and

scaling an original net delay in the victim net obtained from said static timing analysis, with the ratio (d′

_Elmore/d_Elmore), to obtain an estimate of net delay in the repaired version of said victim net.

6. The computer-implemented method of claim 2 wherein said computing of change in cell delay comprises:

looking up a cell delay d1 of said victim net driver cell from a library;

looking up another cell delay d2 of an enlarged version of said victim net driver cell, from said library; and

scaling an original cell delay in the victim net obtained from said static timing analysis, with the ratio (d2/d1), to obtain an estimate of cell delay in the repaired version of said victim net.

7. The computer-implemented method of claim 1 wherein said choosing comprises:

formulating an NP complete problem comprising identification of contribution of each net in said set to repair of said path and to repair of a plurality of additional paths, each additional path comprising at least one net in said set; and

applying a predetermined heuristic iteratively to solve said NP complete problem.

8. The computer-implemented method of claim 7 wherein:

said predetermined heuristic identifies a to-be-repaired net at each iteration by maximizing a total reduction in delay for all paths passing through said to-be-repaired net.

9. The computer-implemented method of claim 7 wherein:

said NP complete problem is expressed as an Integer Linear Programming (ILP) problem.

10. A computer-implemented method of designing layouts of integrated circuits, the method comprising:

performing a place and route operation on a netlist of an integrated circuit, to produce a layout for the integrated circuit;

extracting parasitics of the integrated circuit based on the netlist and the layout;

performing static noise analysis on the netlist based on the layout and the parasitics, to estimate noise behavior of the netlist and to identify at least one violation by said noise behavior of a corresponding noise requirement on a victim net in the netlist;

performing engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said noise behavior, and said violation by;

(a) identifying a group of aggressor nets capacitively coupled to said victim net;

(b) forming a set of candidate nets including said group of aggressor nets and said victim net;

(c) estimating at least one change in noise behavior of each candidate net required to be made to overcome said violation; and

(d) choosing a subset of candidate nets to be repaired from among said set of candidate nets, based on said change estimated in (c);

generating an ECO constraint on noise behavior of said subset, wherein said ECO constraint is to be satisfied by a ECO repair technique to be used to correct said violation;

automatically selecting said ECO repair technique from among a plurality of ECO repair techniques, based on said ECO constraint; and

repairing said layout by applying said ECO repair technique to generate a modified layout corrected for said violation;

wherein said estimating in (c) comprises computing a change in crosstalk delay in at least said victim net by using values of total resistance and total capacitance of said victim net and an aggressor net, and input capacitance of receiver cells of said victim net and said aggressor net, and resistance of said victim net'"'"'s driver cell and resistance of said aggressor net'"'"'s driver cell.

11. The computer-implemented method of claim 10 wherein said estimating comprises:

applying a closed form equation for said aggressor net, to obtain a maximum height of a bump arising in said victim net due to crosstalk from said aggressor net;

repeating said applying, to obtain at least one additional maximum height of said bump in said victim net, due to crosstalk from at least one additional aggressor net capacitively coupled to said victim net;

summing up maximum heights of said bump in said victim net obtained by said applyings, to obtain a first total of maximum heights of said bump in said victim net;

repeating said applying with an enlarged version of said victim net driver cell, thereby to obtain a smaller maximum height of said bump for each aggressor net capacitively coupled to a repaired version of said victim net, wherein the repaired version of said victim net comprises the enlarged version of said second cell;

repeating said summing up to obtain a second total of smaller maximum heights of said bump in said repaired victim net; and

scaling an original height of the bump in said victim net obtained from said static timing analysis, with a ratio of said second total to said first total, to obtain an estimate of a final height of said bump in the repaired version of said victim net.

12. The computer-implemented method of claim 10 wherein said choosing comprises:

formulating an NP complete problem comprising identification of contribution of each net in said set to repair of said path and to repair of a plurality of additional paths, each additional path comprising at least one net in said set; and

applying a predetermined heuristic iteratively to solve said NP complete problem.

13. The computer-implemented method of claim 12 wherein:

said predetermined heuristic identifies a to-be-repaired net at each iteration by maximizing a total reduction in noise for all paths passing through said to-be-repaired net.

14. A computer-implemented method of designing layouts of integrated circuits, the method comprising:

receiving a netlist of an integrated circuit to be fabricated;

performing a place and route operation on the netlist, to produce a layout for the integrated circuit;

extracting parasitics of the integrated circuit based on the netlist and the layout;

performing analysis of at least one of (timing and noise) on the netlist based on the layout and the parasitics, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement;

performing engineering change order (ECO) analysis on the netlist based on the layout, the parasitics, said behavior, and said violation;

generating an ECO constraint on said behavior based on a result of said performing ECO analysis;

testing on said layout each ECO repair technique in a plurality of ECO repair techniques successively, until an ECO repair technique is found to satisfy said ECO constraint; and

repairing said layout by applying said ECO repair technique found to be satisfactory by said testing, to generate a modified layout corrected for said violation;

wherein said performing ECO analysis comprises estimating at least one change in behavior of a first net in the netlist to overcome said violation; and

wherein said estimating comprises computing a change in crosstalk delay in said first net by using values of total resistance and total capacitance of said first net and a second net in said netlist, and the input capacitance of receiver cells of said first net and said second net, and resistance of said first net'"'"'s driver cell and resistance of said second net'"'"'s driver cell.

15. The computer-implemented method of claim 14 wherein said performing ECO analysis comprises:

identifying a plurality of victim nets contributing to said behavior said plurality of victim nets comprising said first net.

forming a set of candidate nets including said plurality of victim nets and a plurality of aggressor nets, wherein each aggressor net is capacitively coupled to a victim net said plurality of aggressor nets comprising said second net.

choosing a subset of candidate nets to be repaired from among said set of candidate nets, based on said change estimated in said performing ECO analysis.