Integrated circuit package system including stacked die

• US 7,456,088 B2
• Filed: 01/04/2006
• Issued: 11/25/2008
• Est. Priority Date: 01/04/2006
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Ha, Jong-Woo, Park, Soo-San, Kwon, Hyeog Chan, Lee, Sang-Ho
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US11/306,627
• Publication Number:
  US 20070158833A1
• Time in Patent Office: 1,056 Days
• Field of Search: 257/680, 257/686, 257/701, 257/705, 257/707, 257/777
• US Class Current: 438/613
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 25/03 all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

An integrated circuit package system is provided including providing a wafer with bond pads formed on the wafer. A solder bump is deposited on one or more bond pads. The bond pads and the solder bump are embedded within a mold compound formed on the wafer. A groove is formed in the mold compound to expose a portion of the solder bump. The wafer is singulated into individual die structures at the groove.

Claims

1. An integrated circuit package system comprising:

providing a wafer with bond pads formed on the wafer;

depositing a solder bump on one or more bond pads;

embedding the bond pads and the solder bump within a mold compound formed on the wafer;

forming a groove in the mold compound to expose a portion of the solder bump; and

singulating the wafer at the groove into individual die structures.

2. The system as claimed in claim 1 wherein forming the groove further comprises:

removing a top portion of the mold compound and a top portion of a solder bump associated with a bond pad.

3. The system as claimed in claim 2 further comprising:

exposing the top portion of two adjacent solder bumps.

4. The system as claimed in claim 1 wherein singulating further comprises:

cutting the wafer and the mold compound between two adjacent bond pads.

5. The system as claimed in claim 1 further comprising:

planarizing the bottom exposed surface of the wafer.

6. The system as claimed in claim 1 further comprising:

providing a printed circuit board; and

connecting the exposed portion of the solder bump to the printed circuit board with electrical connectors,

wherein a combined height of the mold compound and the wafer is at least greater than a height of the electrical connectors.

7. The system as claimed in claim 6 further comprising:

stacking a second semiconductor structure on the mold compound; and

connecting the second semiconductor structure to the printed circuit board.

8. The system as claimed in claim 6 further comprising:

encapsulating the wafer, the mold compound, and the electrical connectors with an encapsulant.

9. The system as claimed in claim 7 further comprises:

providing a layer of film laminate on the mold compound and under the second semiconductor structure.

10. The system as claimed in claim 6 further comprising:

forming solder balls on the bottom surface of the printed circuit board.