Super lattice modification of overlying transistor
First Claim
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1. A semiconductor device comprising:
- a substrate comprising silicon or silicon carbide;
an upper buffer region comprised of a group III-nitride semiconductor;
a lower buffer region over said substrate comprised of a group III-nitride semiconductor;
a heterojunction region comprised of a group III-nitride semiconductor and positioned upon said upper buffer region; and
a superlattice positioned between said lower buffer region and said upper buffer region, wherein said superlattice comprises individual layers of GaN and AlxGa1-xN;
wherein a group III-nitride semiconductor includes at least nitrogen and a group III element from the list consisting of Al, In, and Ga.
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Abstract
The invention provides a device having a substrate, a buffer region positioned upon the substrate, wherein the buffer region has an upper buffer region and a lower buffer region, a heterojunction region positioned upon the buffer region, and a superlattice positioned between the lower buffer region and the upper buffer region, wherein the device is configured to function as a heterojunction field effect transistor.
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Citations
28 Claims
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1. A semiconductor device comprising:
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a substrate comprising silicon or silicon carbide; an upper buffer region comprised of a group III-nitride semiconductor; a lower buffer region over said substrate comprised of a group III-nitride semiconductor; a heterojunction region comprised of a group III-nitride semiconductor and positioned upon said upper buffer region; and a superlattice positioned between said lower buffer region and said upper buffer region, wherein said superlattice comprises individual layers of GaN and AlxGa1-xN; wherein a group III-nitride semiconductor includes at least nitrogen and a group III element from the list consisting of Al, In, and Ga. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A device comprising:
- a substrate;
a buffer region positioned upon said substrate, wherein said buffer region comprises an upper buffer region and a lower buffer region;
a heterojunction region positioned upon said buffer region; and
a superlattice positioned between said lower buffer region and said upper buffer region, wherein said superlattice comprises individual layers of GaN and AlxGa1-xN, wherein said device is configured to function as a heterojunction field effect transistor, wherein said heterojunction region comprises a first layer and a second layer, wherein said second layer is positioned directly above said upper buffer region, and said first layer is positioned directly above said second layer, and wherein said first layer and said second layer both comprise AlyGa1-yN, where y has a value of from about 0.1 to 1. - View Dependent Claims (10, 11)
- a substrate;
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12. A device comprising:
- a substrate;
a buffer region positioned upon said substrate, wherein said buffer region comprises an upper buffer region and a lower buffer region;
a heterojunction region positioned upon said buffer region; and
a superlattice positioned between said lower buffer region and said upper buffer region, wherein said superlattice comprises individual layers of GaN and AlxGa1-xN, wherein said device is configured to function as a heterojunction field effect transistor, wherein said heterojunction region comprises AlbGa1-bN, where b has a value of from about 0.1 to 1. - View Dependent Claims (13, 14)
- a substrate;
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15. group A III-nitride device comprising:
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a substrate comprising sapphire; an upper group III-nitride semiconductor buffer region; a lower group III-nitride semiconductor buffer region; a group III-nitride semiconductor heterojunction region positioned upon said upper buffer region; and a superlattice positioned between said lower buffer region and said upper buffer region, wherein said superlattice comprises individual layers of GaN and AlxGa1-xN;
wherein said group III-nitride semiconductor includes at least nitrogen and an element from a group consisting of Al, In, Ga. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A device comprising:
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a substrate comprising silicon carbide; an upper group III-nitride semiconductor buffer region; a lower group III-nitride semiconductor buffer region; a group III-nitride semiconductor heterojunction region positioned upon said upper buffer region; and a superlattice positioned between said lower buffer region and said upper buffer region, wherein said superlattice comprises individual layers of GaN and AlxGa1-xN; wherein said group III-nitride semiconductor includes at least nitrogen and an element from the group consisting of Al, In and Ga. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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Specification