Fabricated U-shaped capacitor for a digital-to-analog converter

• US 7,456,462 B1
• Filed: 03/07/2006
• Issued: 11/25/2008
• Est. Priority Date: 03/07/2006
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Alvand Technologies, Inc. (Renesas Electronics Corporation)
• Inventors: Keramat, Mansour, Heshami, Mehrdad
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): Tran; Tan N
• Application Number:
  US11/371,145
• Time in Patent Office: 994 Days
• Field of Search: 257/303, 257/306, 257/307, 257/296, 257/298, 257/300, 257/308, 257/E21.648, 341/150
• US Class Current: 257/307
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/87 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A layered capacitor having top and bottom plates formed from multiple layers. The capacitor has a bottom layer comprising a bottom plate portion and at least one upper layer, each upper layer comprising top and bottom plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a U-shaped bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor device. The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, which may be used in a SAR ADC.

Claims

1. A capacitor device array comprising:

at least two capacitor devices arranged in columns and rows,

wherein each capacitor device is formed from a bottom layer and a plurality of upper layers above the bottom layer, each capacitor device comprising;

a U-shaped bottom plate comprising a plurality of bottom plate portions; and

a top plate comprising a plurality of top plate portions, wherein;

the entirety of the bottom layer comprises a bottom plate portion of the U-shaped bottom plate;

each upper layer comprises a top plate portion located between two separate bottom plate portions, the two separate bottom plate portions being unconnected across the upper layer;

the U-shaped bottom plate comprises a bottom side formed from the bottom layer and right and left sides formed from the plurality of upper layers and a first set of vias, the right and left sides being connected to each other by the bottom side;

the top plate is formed from the plurality of upper layers and a second set of vias, the top plate being surrounded by the U-shaped bottom plate on the bottom, right, and left sides of the top plate; and

the top plate is not coupled to the U-shaped bottom plate, the top plate and U-shaped bottom plate being separated by a distance,

wherein all top plates of capacitor devices of a same column of the array are connected to form a unified top plate; and

a set of connectors connecting the unified top plates of different columns of the array.

2. The capacitor device array of claim 1, wherein:

for each capacitor device in the array, the top plate extends past the length of the bottom plate to connect to a top plate of an adjacent capacitor device in the same column of the array.

3. The capacitor device array of claim 1, further comprising:

a set of connectors connecting the top plates of capacitor devices of a same column of the array.

4. The capacitor device array of claim 1, wherein the capacitor device array is used in a capacitive digital-to-analog converter (DAC).

5. The capacitor device array of claim 4, wherein:

the capacitive DAC has a resolution of a predetermined number of bits, from a least significant bit (LSB) to a most significant bit (MSB); and

the capacitor devices are arranged in a two dimensional array having a predetermined number of columns and rows, the predetermined number of columns and rows being dependent on the resolution of the capacitive DAC.

6. The capacitor device array of claim 5, wherein the architecture of the DAC is a segmented architecture.

7. The capacitor device array of claim 5, wherein:

the architecture of the DAC is a binary weighted architecture;

the at least two capacitor devices have approximately equal capacitance values;

a single capacitor device is coupled to the DAC for the LSB; and

two capacitor devices are coupled to each other and coupled to the DAC for the next LSB.

8. A capacitive digital-to-analog converter (DAC) comprising:

a capacitor device array comprising at least two capacitor devices arranged in columns and rows,

wherein each capacitor device is formed from a bottom layer and a plurality of upper layers above the bottom layer, each capacitor device comprising;

a U-shaped bottom plate comprising a plurality of bottom plate portions; and

a top plate comprising a plurality of top plate portions, wherein;

the entirety of the bottom layer comprises a bottom plate portion of the U-shaped bottom plate;

each upper layer comprises a top plate portion located between two separate bottom plate portions, the two separate bottom plate portions being unconnected across the upper layer;

the U-shaped bottom plate comprises a bottom side formed from the bottom layer and right and left sides formed from the plurality of upper layers and a first set of vias, the right and left sides being connected to each other by the bottom side;

the top plate is formed from the plurality of upper layers and a second set of vias, the top plate being surrounded by the U-shaped bottom plate on the bottom, right, and left sides of the top plate; and

the top plate is not coupled to the U-shaped bottom plate, the top plate and U-shaped bottom plate being separated by a distance,

wherein all top plates of capacitor devices of a same column of the array are connected to form a unified top plate; and

a set of connectors connecting the unified top plates of different columns of the array; and

one or more processing circuits coupled to the capacitor device array for converting a digital code into an analog signal using the capacitor device array.

9. The capacitive DAC of claim 8, wherein:

the capacitive DAC has a resolution of a predetermined number of bits, from a least significant bit (LSB) to a most significant bit (MSB); and

the capacitor devices are arranged in a two dimensional array having a predetermined number of columns and rows, the predetermined number of columns and rows being dependent on the resolution of the capacitive DAC.

10. The capacitive DAC of claim 9, wherein the architecture of the DAC is a segmented architecture.

11. The capacitive DAC of claim 9, wherein:

the architecture of the DAC is a binary weighted architecture;

the at least two capacitor devices have approximately equal capacitance values;

a single capacitor device is used for the LSB; and

two capacitor devices are coupled to each other and used for the next LSB.

12. The capacitive DAC of claim 8, wherein the capacitive DAC is used in a successive approximation analog-to-digital converter (SAR ADC).