Semiconductor device including high-k insulating layer and method of manufacturing the same

• US 7,456,468 B2
• Filed: 01/18/2006
• Issued: 11/25/2008
• Est. Priority Date: 01/18/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Sang-Moo, Han, Jeong-Hee, Jeon, Sang-Hun, Hwang, Hyun-Sang, Kim, Chung-Woo, Park, Sung-Ho, Choi, Sung-Kyu
• Primary Examiner(s): Jackson; Jerome
• Assistant Examiner(s): Diaz; Jose R
• Application Number:
  US11/335,431
• Publication Number:
  US 20060157754A1
• Time in Patent Office: 1,042 Days
• Field of Search: 257/324
• US Class Current: 257/324
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02156 the material containing at least one rare earth element, e.g. silicate of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02159 the material containing zirconium, e.g. ZrSiOx
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

Claims

1. A semiconductor memory device comprising:

a first dopant area and a second dopant area, the first dopant area and the second dopant areas disposed in a semiconductor substrate;

an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including an amorphous material comprising at least one of an Hf silicate, a Zr silicate, a Y silicate, and a Ln silicate; and

a gate electrode layer disposed on the insulating layer,

wherein the insulating layer comprises;

a tunneling oxide layer disposed in contact with the first dopant area and the second dopant area;

a data storing layer disposed on the tunneling oxide layer; and

a blocking oxide layer disposed on the data storing layer,

wherein the tunneling oxide layer consists of the amorphous material having the chemical formula ((Hf, Zr, Y or Ln)O₂)_x(SiO₂)<sub>1−

x</sub>, where (0.03≦

x≦

0.26).

2. The semiconductor memory device of claim 1, the amorphous material having a dielectric constant that is greater than 3.9 and less than or equal to 10.

3. The semiconductor memory device of claim 1, the insulating layer comprising one of Al and N.

4. The semiconductor memory device of claim 1, the insulating layer comprising the Hf silicate.

5. The semiconductor memory device of claim 1, the insulating layer comprising the Zr silicate.

6. The semiconductor memory device of claim 1, the insulating layer comprising the Y silicate.

7. The semiconductor memory device of claim 1, the insulating layer comprising the Ln silicate.