Top drain fet with integrated body short

• US 7,456,470 B2
• Filed: 09/29/2005
• Issued: 11/25/2008
• Est. Priority Date: 10/01/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Jones, David Paul
• Primary Examiner(s): Landau; Matthew C.
• Assistant Examiner(s): Kim; Jay C
• Application Number:
  US11/238,207
• Publication Number:
  US 20060113589A1
• Time in Patent Office: 1,153 Days
• Field of Search: 257/329, 257/330, 257/331, 257/341, 257/263, 257/332, 257/E27.091, 257/E29.201, 257/E29.257, 257/E29.26
• US Class Current: 257/331
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors

Abstract

A top drain MOSgated device has its drain on the top of semiconductor die and its source on the bottom of the die substrate. Parallel spaced trenches extend from the die top surface through a drift region, a channel region and terminate on the substrate region. The bottoms of each trench receive a silicide conductor to short the substrate source to channel regions. The silicide conductors are then insulated at their top surfaces and gate electrodes are placed in the same trenches as those receiving the channel/source short.

Claims

1. A top drain MOSgated device, comprising a semiconductor die having a top and bottom surface comprising a substrate of a first conductivity type extending from said bottom surface;

a first region of said first conductivity type over said substrate, a region of a second conductivity type over said first region of said first conductivity type;

a channel region of said second conductivity type atop said region of said second conductivity type, said channel region being less conductive than said region of said second conductivity type;

a drift region of said first conductivity type atop said channel region;

a plurality of parallel spaced gate trenches extending from said top surface through said drift region, said channel region, said region of said second conductivity type and said first region of said first conductivity type;

a second region of said first conductivity type formed adjacent each said gate trench and inside said region of said second conductivity type spaced from said first region by a portion of said region of said second conductivity type, a third region of said first conductivity type formed partially in said region of said second conductivity type and extending from said second region into said channel region;

the bottom of each of said gate trenches having a conductive silicide short electrically connecting said substrate to said first region of said first conductivity type, said region of said second conductivity type, and said second region of said first conductivity type;

a bottom insulating mass in the bottom of each of said gate trenches;

a gate oxide liner lining the walls of each of said gate trenches adjacent at least a portion of a depth of said channel region;

a conductive gate mass within each of said gate trenches and bounded on its bottom by said bottom insulating mass and at its sides by said gate oxide liner;

a top insulation mass substantially filling a top of each of said gate trenches above the top of each of said conductive gate masses; and

a top drain electrode disposed on said top surface and in contact with said drift region between said gate trenches; and

a bottom source electrode connected to said bottom surface.

2. The device of claim 1, wherein said first conductivity type is an N type.

3. The device of claim 1, wherein said conductive gate mass is formed of conductive polysilicon.

4. The device of claim 1, which further includes a contact diffusion of increased concentration of carriers of said first conductivity type atop said drift region.

5. The device of claim 1, which further includes a conductive silicide layer atop said drift region.