Semiconductor device and manufacturing method thereof

• US 7,456,472 B2
• Filed: 12/07/2004
• Issued: 11/25/2008
• Est. Priority Date: 09/30/2004
• Status: Expired due to Fees

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Inaba, Satoshi
• Primary Examiner(s): Le; Thao P.
• Application Number:
  US11/005,477
• Publication Number:
  US 20060073647A1
• Time in Patent Office: 1,449 Days
• Field of Search: 257/341, 257/365, 257/366, 257/350, 257/401, 257/288, 257/E27.099, 257/E29.13
• US Class Current: 257/341
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device comprising a multi Fin-FET structure capable of suppressing short channel effects, controlling a threshold voltage, driving a high current, and operating in a high-speed comprises a source region and a drain region disposed on a semiconductor substrate, a plurality of fins interconnecting the source region and drain region, a first gate electrode disposed on the semiconductor substrate and to one side face of each fin, a second gate electrode disposed on the semiconductor substrate and to the other side face of the fin to face the first gate electrode, and separated from the first gate electrode, a plurality of first pad electrodes connected to respective first gate electrode, a first wiring interconnecting the plurality of first pad electrodes, a plurality of second pad electrodes connected to respective second gate electrode, and a second wiring interconnecting the plurality of second pad electrodes.

Claims

1. A semiconductor device comprising:

a source region and a drain region disposed on a semiconductor substrate;

a plurality of fins which interconnect the source region and the drain region;

a plurality of first gate electrodes, each first gate electrode disposed on the semiconductor substrate and to one side face of each fin;

a plurality of second gate electrodes, each second gate electrode disposed on the semiconductor substrate and to the other side face of the fin to face a respective of the first gate electrodes with respect to the fin, and separated from the first gate electrodes;

a plurality of first pad electrodes connected to respective of the first gate electrodes;

a first wiring which interconnects the plurality of first pad electrodes;

a plurality of second pad electrodes connected to respective of the second gate electrodes; and

a second wiring which interconnects the plurality of second pad electrodes.

2. The semiconductor device according to claim 1, wherein potentials of the first gate electrodes are controlled independently of the second gate electrodes.

3. The semiconductor device according to claim 1, further comprising a plurality of stretched regions stretched from the source region or the drain region toward the first or second gate electrodes, and formed to be connected to one or two adjacent fins.

4. The semiconductor device according to claim 3, wherein the stretched region from the source region and the stretched region from the drain region are alternately arranged.

5. The semiconductor device according to claim 3, wherein the stretched region is formed only from the source region.

6. The semiconductor device according to claim 3, wherein the first and second pad electrodes are arranged not to overlap with the stretched region.

7. The semiconductor device according to claim 2, further comprising a plurality of stretched regions stretched from the source region or the drain region toward the first or second gate electrode, and formed to be connected to one or two adjacent fins.

8. The semiconductor device according to claim 7, wherein the stretched regions from the source region and the stretched regions from the drain region are alternately arranged.

9. The semiconductor device according to claim 7, wherein the stretched regions are formed only from the source region.

10. The semiconductor device according to claim 7, wherein the first and second pad electrodes are arranged not to overlap with the stretched regions.

11. The semiconductor device according to claim 1, wherein a channel is formed only in one side face of each fin.

12. The semiconductor device according to claim 1, wherein the plurality of first gate electrodes are arranged alternately with the plurality of second gate electrodes.

13. The semiconductor device according to claim 1, wherein each of the plurality of second gate electrodes is alternately arranged with each of the plurality of first gate electrodes disposing each one of the plurality of fins inbetween, wherein the plurality of the first pad electrodes are disposed in a source region side of the first or second gate electrodes, and wherein the plurality of the second pad electrodes are disposed in a drain region side of the first or second gate electrodes.

14. The semiconductor device according to claim 13, further comprising a plurality of stretched regions each of which are stretched from the source region or the drain region toward the first or second gate electrode and formed to be connected to two adjacent fins.

15. The semiconductor device according to claim 14, wherein the plurality of fins include a first fin, a second fin disposed adjacent to the first fin, and a third fin disposed adjacent to the second fin, and wherein the plurality of stretched regions include a first stretched region stretched from the drain region toward the first gate electrode and connected to the first fin and the second fin and a second stretched region stretched from the source region toward the second gate electrode and connected to the second fin and the third fin.

16. The semiconductor device according to claim 13, further comprising a plurality of stretched regions, wherein the plurality of fins include a first fin, a second fin disposed adjacent to the first fin, and a third fin disposed adjacent to the second fin, and wherein the plurality of stretched regions include a first stretched region stretched from the drain region toward the first gate electrode and connected to the first fin and the second fin, and a second stretched region stretched from the source region toward the second gate electrode and connected to the second fin and the third fin.

17. The semiconductor device according to claim 3, wherein the plurality of fins include a first fin, a second fin disposed adjacent to the first fin, and a third fin disposed adjacent to the second fin, and wherein the plurality of stretched regions include a first stretched region stretched from the drain region toward the first gate electrode and connected to the first fin and the second fin, and a second stretched region stretched from the source region toward the second gate electrode and connected to the second fin and the third fin.

18. The semiconductor device according to claim 5, wherein a distance between the first and second gate electrodes and the source region is larger than a distance between the first and second gate electrodes and the drain region.