Phase detection circuit, resolver/digital converter using the circuit, and control system using the converter

• US 7,456,603 B2
• Filed: 07/18/2006
• Issued: 11/25/2008
• Est. Priority Date: 07/19/2005
• Status: Active Grant

• Current Assignee: Hitachi Astemo Ltd. (Hitachi, Ltd.)
• Original Assignee: Hitachi, Ltd.
• Inventors: Kanekawa, Nobuyasu, Oyama, Katsuya, Koseki, Tomonobu, Sasaki, Shoji
• Primary Examiner(s): Leykin; Rita
• Application Number:
  US11/488,158
• Publication Number:
  US 20070029955A1
• Time in Patent Office: 861 Days
• Field of Search: 318/807, 318/607, 341/112, 341/116
• US Class Current: 318/807
• CPC Class Codes: G01D 5/2073 by movement of a single coil with respect to two or more coils
• CPC Class Codes: H03M 1/485 for position encoding, e.g. using resolvers or synchros

Abstract

A small-sized and low-cost phase detection circuit which has improved noise immunity. The phase detection circuit comprises a multiplier for multiplying an input signal by a reference signal and outputting a first signal, an integration circuit for integrating the first signal and outputting a second signal, a phase estimation circuit for estimating phase information based on the second signal, and a reference signal generation circuit for generating the reference signal based on the estimated phase information. Since the phase is detected based on information representing an entire waveform, the influence of local noise can be diluted and noise immunity can be improved.

Claims

1. A phase detection circuit comprising:

a first multiplier for multiplying an input signal by a first reference signal and outputting a first signal;

a first integration circuit for integrating the first signal and outputting a second signal;

a phase estimation circuit for estimating phase information based on the second signal; and

a first reference signal generation circuit for generating the first reference signal based on the estimated phase information.

2. The phase detection circuit according to claim 1, wherein the phase information is an output signal of said phase detection circuit.

3. The phase detection circuit according to claim 1, wherein said phase detection circuit detects the phase information based on information representing an entire waveform of the input signal.

4. The phase detection circuit according to claim 1, wherein the first reference signal generated by said first reference signal generation circuit has a discrete value.

5. The phase detection circuit according to claim 4, wherein the first reference signal generated by said first reference signal generation circuit has a binary value.

6. The phase detection circuit according to claim 4, wherein the first reference signal generated by said first reference signal generation circuit has a ternary value.

7. The phase detection circuit according to claim 6, wherein the first reference signal generated by said first reference signal generation circuit is +1 in a first range covering a phase angle width of 120°

, 0 in a second range covering a succeeding phase angle width of 60°

, −

1 in a third range covering a succeeding phase angle width of 120°

, and 0 in a fifth range covering a succeeding phase angle width of 60°

.

8. The phase detection circuit according to claim 1, wherein a phase difference of 90°

exists between a phase indicated by the image information outputted from said phase estimation circuit and a phase of the first reference signal.

9. The phase detection circuit according to claim 8, wherein said phase estimation circuit increases and decreases the phase information depending on a polarity of the second signal outputted from said first integration circuit.

10. The phase detection circuit according to claim 1, wherein said phase detection circuit further comprises a first comparison circuit, and

said first comparison circuit compares a predetermined value with a value of the second signal outputted from said first integration circuit, and determines the occurrence of an abnormal state when the value of the second signal deviates from a predetermined range.

11. The phase detection circuit according to claim 10, wherein said first comparison circuit determines the occurrence of an abnormal state when the value of said second signal deviates from the predetermined range for a period of not shorter than a preset duration time.

12. The phase detection circuit according to claim 11, wherein said predetermined range is set plural, and

said preset duration time is set for each of the plural predetermined ranges.

13. The phase detection circuit according to claim 10, further comprising:

a second reference signal generation circuit for generating a second reference signal based on the phase information;

a second multiplier for multiplying the input signal by a second reference signal and outputting a third signal;

a second integration circuit for integrating the third signal and outputting a fourth signal; and

a second comparison circuit for comparing the fourth signal with a predetermined range and determining the occurrence of an abnormal state when the fourth signal deviates from the predetermined range.

14. The phase detection circuit according to claim 13, wherein a phase difference of 90°

exists between a phase of the first reference signal outputted from said first reference signal generation circuit and a phase indicated by the image information outputted from said phase estimation circuit.

15. The phase detection circuit according to claim 14, wherein when an output value of said second integration circuit is negative, the phase information outputted from said phase estimation circuit is increased 90°

.

16. A resolver/digital converter receiving at least two signals from a resolver and comprising a phase shift circuit, a subtraction circuit, and a phase detection circuit,

wherein one signal from said resolver is inputted to said phase shift circuit in which a phase of the one signal is shifted,

an output of said phase shift circuit is subtracted from the other signal from said resolver in said subtraction circuit, and

an output of said subtraction circuit is inputted to said phase detection circuit which detects a phase of the output of said subtraction circuit and outputs the detected phase as information indicating a rotational angle of said resolver,

said phase detection circuit being the phase detection circuit according to claim 1.