Liquid crystal display panel and testing and manufacturing methods thereof

• US 7,456,647 B2
• Filed: 06/16/2006
• Issued: 11/25/2008
• Est. Priority Date: 07/19/2005
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Jin, Jung, Min Kyung
• Primary Examiner(s): Nguyen; Ha
• Assistant Examiner(s): Nguyen; Trung Q
• Application Number:
  US11/454,463
• Publication Number:
  US 20070018680A1
• Time in Patent Office: 893 Days
• Field of Search: 324/158.1, 324750-765, 324/537, 324/770, 345/3, 345/5, 345/87, 345 98-100, 349 40- 47, 714718-720
• US Class Current: 324/760.01
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A liquid crystal display (LCD) panel simplifying its testing and manufacturing. The LCD panel includes (formed on a substrate) gate lines, data lines, and pixels including pixel transistors. The LCD panel further includes a plurality test transistors (e.g., data test transistors for driving the odd and even data lines) formed in a package region of a driving IC (integrated circuit) configured to drive the data lines. The plurality of test transistors may be selectively activated (turned ON) during testing before the driving integrated circuit (Driver IC package) is attached (e.g., fixed) to the driving IC package region. The LCD panel may further include a plurality of gate test transistors configured to drive the odd and even gate lines.

Claims

1. A liquid crystal display panel, comprising:

gate lines formed on a substrate;

data lines intersecting the gate lines;

a plurality of pixel transistors, each pixel transistor connected to a gate line and to a data line;

a plurality of pixel electrodes formed in the intersections of the data lines and the gate lines, each pixel electrode connected to a respective pixel transistor; and

a plurality of data test transistors configured to drive the data lines,

wherein the plurality data test transistors are formed in a package region of a driving integrated circuit.

2. The liquid crystal display panel of claim 1, wherein the package region is configured to receive a driving integrated circuit chip.

3. The liquid crystal display panel of claim 2, wherein the plurality of data test transistors is configured to be turned ON or OFF based on whether or not the liquid crystal display panel currently comprises the driving integrated circuit.

4. The liquid crystal display panel of claim 1, wherein the plurality of data test transistors are OFF when the liquid crystal display panel comprises the driving integrated circuit.

5. The liquid crystal display panel of claim 4, further comprising:

an odd data test pad and an odd data test line configured to supply a data test signal to the odd data test transistors;

an even data test pad and an even data test line for supplying the data test signal to the even data test transistors; and

a data control line and a data control pad for supplying a control signal to gates of the odd and even data test transistors.

6. The liquid crystal display panel of claim 4, further comprising:

a data test pad and a data test line configured to supply a data test signal to the odd and even data test transistors.

7. The liquid crystal display panel of claim 6, further comprising:

an odd data control line and an odd data control pad for supplying an odd control signal to gates of the odd data test transistors; and

an even data control line and an even data control pad for supplying an even control signal to gates of the even data test transistors.

8. The liquid crystal display panel of claim 4, further comprising:

a data test pad and a data test line configured to supply a data test signal to the data test transistors; and

a data control line and a data control pad for supplying a control signal to gates of the data test transistors.

9. The liquid crystal display panel of claim 1, wherein the plurality of test transistors are OFF when the liquid crystal display panel comprises the driving integrated circuit and the driving integrated circuit is configured to drive the data lines.

10. The liquid crystal display panel of claim 1, wherein the plurality of data test transistors is OFF when the driving integrated circuit is fixed on the liquid crystal display panel.

11. The liquid crystal display panel of claim 1, wherein the plurality of data test transistors includes:

odd data test transistors connected to the odd data lines among the data lines; and

even data test transistors connected to the even data lines among the data lines.

12. The liquid crystal display panel of claim 1, further comprising:

a plurality of gate test transistors connected to the gate lines.

13. The liquid crystal display panel of claim 12, wherein the plurality of gate test transistors include:

odd gate test transistors connected to the odd gate lines among the gate lines; and

even gate test transistors connected to the even gate lines among the gate lines.

14. The liquid crystal display panel of claim 13, further comprising:

an odd gate test line and an odd gate test pad configured to supply a gate test signal to the odd gate test transistors;

an even gate test line and an even gate test pad configured to supply the gate test signal to the even gate test transistors;

an odd gate control line and an odd gate control pad configured to supply a control signal to the gates of the odd gate test transistors; and

an even gate control line and an even gate control pad configured to supply the control signal to the gates of the even gate test transistors.

15. The liquid crystal display panel of claim 13, further comprising:

a gate test line and a gate test pad configured to supply a gate test signal to the odd and even gate test transistors;

an odd gate control line and an odd gate control pad configured to supply a control signal to the gates of the odd gate test transistors; and

an even gate control line and an even gate control pad configured to supply the control signal to the gates of the even gate test transistors.

16. The liquid crystal display panel of claim 13, further comprising:

an odd gate test line and an odd gate test pad configured to supply a gate test signal to the odd gate test transistors;

an even gate test line and an even gate test pad configured to supply the gate test signal to the even gate test transistors;

a gate control line and a gate control pad configured to supply a control signal to the gates of the odd and even gate test transistors.

17. The liquid crystal display panel of claim 1, further comprising a gate driver formed on the substrate configured to sequentially drive the gate lines.

18. The liquid crystal display panel of claim 17, further comprising a signal supplying pad formed in the package region, configured to supply a driving signal to the gate driver.

19. The liquid crystal display panel of claim 18, further comprising a test signal supplying pad connected commonly with the signal supplying pad, configured to supply a test signal during a testing process.