Flexible cell configuration for multi-processor systems

• US 7,457,128 B2
• Filed: 07/22/2005
• Issued: 11/25/2008
• Est. Priority Date: 07/22/2005
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Peterson, Eric C.
• Primary Examiner(s): Bui; Hung S
• Application Number:
  US11/187,302
• Publication Number:
  US 20070019390A1
• Time in Patent Office: 1,222 Days
• Field of Search: 361748-749, 361/679, 361/600, 361784-789, 174/250, 174/68.1, 174/261, 174/262
• US Class Current: 361/728
• CPC Class Codes: G06F 1/18 Packaging or power distribution
• CPC Class Codes: G06F 1/184 Mounting of motherboards
• CPC Class Codes: G06F 1/185 Mounting of expansion boards
• CPC Class Codes: G06F 1/186 Securing of expansion boards in correspondence to slots provided at the computer enclosure

Abstract

A cell configuration for a multi-processor system comprises: a first circuit board comprising: a single processor; a single processor agent coupled electrically to the single processor; and a plurality of memory modules coupled electrically to the single processor agent; a second circuit board comprising: a single processor; a single processor agent coupled electrically to the single processor; and a plurality of memory modules coupled electrically to the single processor agent; and wherein the first and second circuit boards are inter-connected in such a manner to form an electrical connection between the single processor of the first circuit board and the single processor agent of the second circuit board and an electrical connection between the single processor of the second circuit board and the single processor agent of the first circuit board.

Claims

1. A cell configuration for a multi-processor system, said cell configuration comprising:

a first circuit board comprising;

a first single processor;

a first single processor agent coupled electrically to said first single processor; and

a plurality of memory modules coupled electrically to said first single processor agent;

wherein memory request from said first processor to said plurality of memory modules passes through said first single processor agent;

a second circuit board comprising;

a second single processor;

a second single processor agent coupled electrically to said second single processor; and

a plurality of memory modules coupled electrically to said second single processor agent;

wherein memory requests from said second processor to said plurality of memory modules passes through said second single processor agent; and

wherein said first and second circuit boards are inter-connected in such a manner to form an electrical connection between the first single processor of said first circuit board and the second single processor agent of said second circuit board allowing memory request from said first processor to pass through said second single processor agent and an electrical connection between the second single processor of said second circuit board and the first single processor agent of said first circuit board allowing memory request from said second processor to pass through said first single processor agent.

2. The cell configuration of claim 1 wherein each first and second circuit board includes at least one power regulation module.

3. The cell configuration of claim 1 wherein each single processor of the first and second circuit boards includes a single processor integrated circuit.

4. The cell configuration of claim 1 wherein each single processor agent of the first and second circuit boards include a single processor agent integrated circuit.

5. The cell configuration of claim 1 wherein each memory module of the plurality of the first and second circuit boards includes a dual in-line memory module.

6. The cell configuration of claim 1 wherein each of the first and second circuit boards includes a plurality of board connectors that are coupled electrically to the single processor and single processor agent of the corresponding board;

and wherein the first and second circuit boards are inter-connected through the plurality of board connectors of each board.

7. The cell configuration of claim 1 wherein the first and second circuit boards are inter-connected through a backplane arrangement.

8. A cell configuration for a multi-processor system, said cell configuration comprising:

two first circuit boards, each first circuit board comprising;

a first single processor;

a first single processor agent coupled electrically to said first single processor; and

a plurality of memory modules coupled electrically to said first single processor agent;

wherein memory requests from said first processor to said plurality of memory modules passes through said first single processor agent;

a second circuit board comprising;

a second processor agent;

a second plurality of memory modules coupled electrically to said second processor agent;

a third processor agent; and

a third plurality of memory modules coupled electrically to said third processor agent; and

wherein said two first circuit boards and said second circuit board are inter-connected together in such a manner to form;

an electrical connection from the single processor of one of said first circuit boards to the processor agent of another of said first circuit boards and to the second and third processor agents of said second circuit board allowing memory requests from said single processor of one of said first circuit boards to pass through said processor agent of another of said first circuit boards and said second and third processor agents of said second circuit board, and

an electrical connection from the first single processor of said other first circuit board to the processor agent of said one first circuit board and to the second and third processor agents of said second circuit board allowing memory requests from said first single processor of said one first circuit board to pass through said processor agent of said one of first circuit board and said second and third processor agents of said second circuit board.

9. The cell configuration of claim 8 wherein each of the first circuit boards and second circuit board includes at least one power regulation module.

10. The cell configuration of claim 8 wherein each single processor of the first circuit boards includes a single processor integrated circuit.

11. The cell configuration of claim 8 wherein each single processor agent of the first and second circuit boards include a single processor agent integrated circuit.

12. The cell configuration of claim 8 wherein each memory module of the plurality of the first and second circuit boards includes a dual in-line memory module.

13. The cell configuration of claim 8 wherein each of the first circuit boards includes a plurality of board connectors that are coupled electrically to the single processor and single processor agent of the corresponding board;

wherein the second circuit board includes a plurality of board connectors that are coupled electrically to the second and third processor agents thereof; and

wherein the first circuit boards and second circuit board are inter-connected through the plurality of board connectors of each board.

14. The cell configuration of claim 8 wherein the first circuit boards and second circuit board are inter-connected through a backplane arrangement.

15. A cell configuration for a multi-processor system, said cell configuration comprising:

three circuit boards, each circuit board comprising;

a single processor;

a single processor agent coupled electrically to said single processor; and

a plurality of memory modules coupled electrically to said single processor agent;

wherein memory requests from said single processor to said plurality of memory modules passes through said single processor agent;

and

wherein said three circuit boards are inter-connected together in such a manner to form an electrical connection from the single processor of each of said three circuit boards to at least one processor agent of the other two of said three circuit boards allowing memory request from said single processor of each of said three circuit boards to pass through said at least one processor agent of the other two of said three circuit boards.

16. The cell configuration of claim 15 wherein the single processor agent of each circuit board is connected to the single processor of both of the other two circuit boards.

17. The cell configuration of claim 15 wherein each single processor of the three circuit boards includes a single processor integrated circuit.

18. The cell configuration of claim 15 wherein each single processor agent of the three circuit boards include a single processor agent integrated circuit.

19. The cell configuration of claim 15 wherein each memory module of the plurality of the three circuit boards includes a dual in-line memory module.

20. The cell configuration of claim 15 wherein each of the three circuit boards includes a plurality of board connectors that are coupled electrically to the single processor and single processor agent of the corresponding board;

and wherein the three circuit boards are inter-connected through the plurality of board connectors of each board.

21. The cell configuration of claim 15 wherein the three circuit boards are inter-connected through a backplane arrangement.

22. A cell configuration for a multi-processor system, said cell configuration comprising:

a first means comprising;

a first single processor;

a first single processor agent for communicating with said first single processor; and

a plurality of memory modules for communicating with said first single processor agent;

wherein memory requests from said first single processor to said plurality of memory modules passes through said first single processor agent;

a second means comprising;

a second single processor;

a second single processor agent for communicating with said second single processor; and

a plurality of memory modules for communicating with said second single processor agent;

wherein memory requests from said second single processor to said plurality of memory modules passes through said second single processor agent; and

said first means being coupled to said second means for permitting communication between said first single processor and said second single processor agent allowing memory requests from said first single processor to pass through said second single processor agent and for permitting communication between said second single processor and said first single processor agent allowing memory requests from said second single processor to pass through said second first processor agent.