Integrated DRAM-NVRAM multi-level memory
First Claim
1. An integrated DRAM-NVRAM memory cell comprising:
- a field effect transistor having a floating body portion; and
a floating plate transistor coupled to the field effect transistor through the floating body portion wherein the floating plate is configured to either accept excess hole charge from the floating body to increase field effect transistor conductance or accept excess electrons from the floating body to decrease field effect transistor conductance.
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Accused Products
Abstract
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.
74 Citations
18 Claims
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1. An integrated DRAM-NVRAM memory cell comprising:
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a field effect transistor having a floating body portion; and a floating plate transistor coupled to the field effect transistor through the floating body portion wherein the floating plate is configured to either accept excess hole charge from the floating body to increase field effect transistor conductance or accept excess electrons from the floating body to decrease field effect transistor conductance. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated DRAM-NVRAM memory cell formed in a substrate, the memory cell comprising:
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a field effect transistor having a floating body portion with a drain region and a first source region located on opposite sides of the floating body; and a floating plate transistor coupled, though the floating body portion, to the field effect transistor and sharing the drain region with the field effect transistor, the floating plate transistor comprising; a second source region, the first and second source regions each adapted to generate a depletion region that are substantially close enough together to create the floating body portion; and a tunneling dielectric formed between the floating plate and the substrate. - View Dependent Claims (10, 11, 12, 13, 14)
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15. An integrated DRAM-NVRAM memory cell formed in a substrate having a pillar defined by two trenches, the memory cell comprising:
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a field effect transistor having a floating body portion with a drain region in the pillar and a first source region formed under a first trench; and a floating plate transistor coupled, through the floating body portion, to the field effect transistor and sharing the drain region with the field effect transistor, the floating plate transistor comprising; a vertical floating plate formed adjacent to a vertical side of the pillar; a control gate formed in the remaining trench and adjacent to the vertical floating plate; a second source region formed under the remaining trench; a tunneling dielectric formed between the floating plate and the pillar; and a charge blocking layer formed between the control gate and the floating plate. - View Dependent Claims (16, 17, 18)
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Specification