Multi-state memory

• US 7,457,162 B2
• Filed: 10/05/2007
• Issued: 11/25/2008
• Est. Priority Date: 08/07/1997
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Fong, Yupin Kawing, Guterman, Daniel C.
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/868,225
• Publication Number:
  US 20080043529A1
• Time in Patent Office: 417 Days
• Field of Search: 365/185.19, 365/185.03, 365/185.18, 365/185.21, 365/185.2, 365/185.22, 365/185.24
• US Class Current: 365/185.19
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Claims

1. A method of programming a multi-state memory having a plurality of non-volatile memory cells, each for storing a plurality of multi-states and organized into an array of rows, and columns, and cell operating circuitry including sense circuitry, wherein one or more selected cells along a row are capable of being read simultaneously, and write circuitry, the method comprising:

selecting one or more memory cells in a row for the concurrent writing of a respective target state from said multi-states; and

concurrently applying one or more programming pulses to said selected memory cells, wherein the amplitude of the initial pulse of said concurrently applied pulses is determined on a cell by cell basis for each of the selected memory cells based on the target state to which the respective selected memory cell is to be written.

2. The method of claim 1, wherein the cell operating circuitry includes steering elements organized in a column oriented manner and select circuitry organized in a row oriented manner, wherein said programming pulses are applied by the write circuitry to the selected memory cells on a respective control gate connected to a corresponding steering element.

3. The method of claim 1, wherein the memory programs the memory in units formed of a plurality of memory cells, where said selected memory cells are from the same programming unit.

4. The method of claim 1, wherein the concurrently applied programming pulses are each an increasing staircase, the initial level the staircase being determined by the target state to which the respective selected memory cell is to be written.

5. The method of claim 4, wherein the memory includes register circuitry for holding a value corresponding to the step of the staircase, the method further comprising incremented said value subsequent to applying each of the pulses.

6. The method of claim 1, where the memory further includes verification circuitry connectable to the selected memory cells, the method further including:

concurrently verifying each of the selected memory cells against the respective target state to which the memory cell is to be written; and

individually terminating the programming of selected memory cells that verified to have been adequately programmed to their respective target states.

7. The method of claim 6, wherein the memory includes first register circuitry for holding first values corresponding respective target states.

8. The method of claim 7, wherein the concurrently applied programming pulses are each an increasing staircase and the memory includes second register circuitry for holding a second value corresponding to the step of the staircase, the method further comprising incremented said value subsequent to applying each of the pulses.

9. The method of claim 8, wherein the first and the second register circuitry are part of the same processing circuit element.

10. The method of claim 8, wherein the first and the second register circuitry are part of different processing circuit elements.

11. The method of claim 6, wherein the memory generates and supplies to the verification circuitry the voltages levels required to verify the multi-states for each of the selected memory cells.

12. The method of claim 11, wherein the memory includes first register circuitry for holding first values corresponding respective target states and the first values are used to determine which of the voltage levels are selected for verifying each of the selected memory cells against the respective target state to which the memory cell is to be written.

13. The method of claim 11, wherein additional voltage level are supplied to the verification circuitry in response to an error indication.