Operating array cells with matched reference cells

• US 7,457,183 B2
• Filed: 10/16/2006
• Issued: 11/25/2008
• Est. Priority Date: 09/16/2003
• Status: Expired due to Term

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Cohen, Guy, Maayan, Eduardo, Lusky, Eli
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US11/580,995
• Publication Number:
  US 20070133276A1
• Time in Patent Office: 771 Days
• Field of Search: 365/210, 365/185.03, 365/185.2
• US Class Current: 365/210.1
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5634 Reference cells

Abstract

A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

Claims

1. A non-volatile memory (“

NVM”

) device comprising;

a set of multi-charge storage region data cells; and

a set of multi-charge-storage-region references cells, wherein at least one of said set of multi-charge storage reference cells has a thermal coefficient substantially correlated with a thermal coefficient value associated with a subset of said set of data cells, wherein said subset of data cells is associated with a specific logical state.

2. The device according to claim 1, wherein said set of data cells is comprised of Nitride Read Only Memory (“

NROM”

) cells.

3. The device according to claim 1, wherein said set of cells is comprised of NROM cells.

4. The device according to claim 1, wherein said set of data cells and set of reference cells are comprised of charge trapping cells.

5. The device according to claim 1, wherein said set of data cells and reference cells are charge trapping cells which store the charge in a non-Nitride material.

6. The device according to claim 1, wherein said set of reference cells includes at least one multi-charge-storage-region cell having a first charge storage region charged to a threshold level associated with a logical state and a second charge storage region partially charged to adjust the at least one cell'"'"'s temperature coefficient.

7. The device according to claim 1, wherein only one storage region of a multi-charge-storage-region cell is used during the device'"'"'s operation.

8. The device according to claim 7, wherein said set of reference cells includes at least one multi-charge-storage-region cell having a first charge storage region charged to a threshold level associated with a logical state and a second charge storage region partially charged to adjust the at least one cell'"'"'s temperature deviations.

9. The device according to claim 6, wherein said set of data cells is comprised of Nitride Read Only Memory (“

NROM”

) cells.

10. The device according to claim 6, wherein said set of reference cells is comprised of NROM cells.

11. A non-volatile memory device comprising multi-charge storage data memory cells and at least one multi-charge storage reference cell, wherein said at least one multi-charge storage reference cell has a negative temperature coefficient;

and during operation, comparing a signal generated by one of said data memory cells to a signal generated by said at least one multi-charge storage reference cell.

12. The device according to claim 11, wherein said at least one multi-charge storage reference cell has at least two storage areas which are in a non-native state.

13. A non-volatile memory device comprising multi-charge storage data memory cells and at least one multi-charge storage reference cell, wherein said at least one multi-charge storage reference cell has a positive temperature coefficient;

and during operation, comparing a signal generated by one of said data memory cells to a signal generated by said at least one multi-charge storage reference cell.

14. The device according to claim 13, wherein said at least one multi-charge storage reference cell has at least two storage areas which are in a non-native state.

15. A non-volatile memory device comprising:

multi-charge storage data memory cells and at least one multi-charge storage reference cell, wherein said at least one multi-charge storage reference cell has a close to zero temperature coefficient; and

during operation, comparing a signal generated by one of said data memory cells to a signal generated by said at least one multi-charge storage reference cell.

16. The device according to claim 15, wherein said at least one multi-charge storage reference cell has at least two storage areas which are in a non-native state.

17. A method of producing a multi-level reference cell for use with a set of data cells, said method comprising:

correlating a thermal coefficient of said multi-level reference cell with a thermal coefficient value associated with the data cells.

18. The method according to claim 17, wherein said correlating comprises programming at least two storage areas of said reference cell.

19. The method according to claim 18, wherein said programming comprises programming a first storage area to a reference level and programming a second storage area to a second programmed level.

20. The method according to claim 19, wherein said reference level and said second programmed level are substantially equal.

21. The method according to claim 19, wherein said reference level and said second programmed level are not equal.

22. The method according to claim 17, wherein said reference cell is selected from the group consisting of a read reference cell, a program verify reference cell and an erase verify reference cell.

23. The method according to claim 17, wherein said reference cell comprises a nitride read only memory (NROM) cell.

24. The method according to claim 17, wherein said reference cell stores charge in a non-nitride layer.

25. The method according to claim 17, wherein said reference cell comprises two storage areas and a physical separation between said two storage areas.

26. The method according to claim 17 wherein said memory cell has more than 2 analog threshold voltage levels.