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Electronic component reliability determination system and method

  • US 7,457,725 B1
  • Filed: 06/24/2003
  • Issued: 11/25/2008
  • Est. Priority Date: 06/24/2003
  • Status: Expired due to Fees
First Claim
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1. An apparatus comprising:

  • one or more processors; and

    a memory coupled to the processors comprising instructions executable by the processors, the processors operable when executing the instructions to;

    identify an inputted reference failure rate for a monitored device, the inputted reference failure rate being a first quotient of an amount of failures associated with a population of the monitored device and an amount of time, the inputted reference failure rate associated with an expected operating temperature for the monitored device and an expected communication capacity utilization for the device;

    communicate with the monitored device while the monitored device is in field operation for determining an actual operating temperature for the monitored device and an actual communication capacity utilization;

    determine a temperature stress adjustment factor using the expected operating temperature and the actual operating temperature;

    determine an electrical stress adjustment factor using the expected communication capacity utilization and the actual communication capacity utilization, wherein the processors are further operable to determine the electrical stress adjustment factor by calculating a difference of the expected communication capacity utilization and the actual communication capacity utilization; and

    output an instantaneous failure rate that is a first mathematical product of the inputted reference failure rate, the temperature stress adjustment factor and the electrical stress adjustment factor.

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