Integrated multimedia system

• US 7,457,890 B2
• Filed: 10/30/2006
• Issued: 11/25/2008
• Est. Priority Date: 10/14/1998
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd., Equator Technologies, Inc. (Pixelworks Incorporated)
• Original Assignee: Hitachi, Ltd.
• Inventors: Miyazaki, Takeshi, Baker, David, O'Donnell, John, Basoglu, Christopher, Nojiri, Toru, Mundkur, Yatin, Lee, Woobin, Gervasio, Gregorio, Cutler, Benjamin, Kojima, Keiji, Kawaguchi, Atsuo, Naik, Vinay, Nishioka, Kiyokazu, Padalkar, Sarang, Deeley, Richard
• Primary Examiner(s): Nguyen; Tanh Q
• Application Number:
  US11/589,695
• Publication Number:
  US 20070130401A1
• Time in Patent Office: 757 Days
• Field of Search: 345501-506, 345/519, 345/520, 710/7, 710 20- 22, 710/29, 710/31, 710 33- 38, 712/1, 712/20, 712/11, 712/16, 712/17, 712/28, 712 32- 36
• US Class Current: 710/20
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06T 15/005 General purpose rendering architectures

Abstract

An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.

Claims

1. An integrated multimedia system having a multimedia processor disposed in an integrated circuit, said system comprising:

a first host processor system coupled to said multimedia processor;

a second local processor disposed within said multimedia processor for controlling the operation of said multimedia processor;

a data transfer switch disposed within said multimedia processor and coupled to said second processor for transferring data to various modules of said multimedia processor, at least one of which is a data cache, wherein said data transfer switch is configured to transfer data in either direction between said data cache and a module within said multimedia processor as requested by said modules;

a data streamer coupled to said data transfer switch, and configured to schedule simultaneous data transfers among the various modules disposed within said multimedia processor, in accordance with corresponding channel allocations;

an interface unit coupled to said data streamer having a plurality of input/output (I/O) device driver units; and

a plurality of external I/O devices coupled to said plurality of I/O device driver units via a multiplexer.

2. The system in accordance with claim 1, wherein each one of said external I/O devices is controlled by a corresponding one of said I/O device driver units.

3. The system in accordance with claim 2, wherein one of said external I/O devices is an NTSC decoder.

4. The system in accordance with claim 2, wherein one of said external I/O devices is an NTSC encoder.

5. The system in accordance with claim 2, wherein one of said external I/O devices is a demodulator unit configured to demodulate wireless communications signals.

6. The system in accordance with claim 5, wherein said demodulator unit communicates with said multimedia processor in accordance with a transport channel interface arrangement.

7. The system in accordance with claim 2, wherein said multimedia processor provides video signals and three dimensional graphic signals to an external video display device.

8. The system in accordance with claim 2, wherein one of said external I/O devices is an ISDN interface.

9. The system in accordance with claim 2, wherein one of said external I/O devices is an audio coder and decoder (CODEC) unit.

10. The system in accordance with claim 1, wherein said data cache is directly coupled to said second local processor and said data transfer switch.

11. The system in accordance with claim 1, wherein said plurality of modules among which said streamer configures to schedule simultaneous data transfers include the interface unit which is capable of controlling the external I/O devices, and a memory controller which is capable of controlling an external memory.

12. The system in accordance with claim 11, wherein said plurality of modules among which said data streamer configures to schedule simultaneous data transfers further include another interface unit which is capable of communicating with said first processor.

13. The system in accordance with claim 1, wherein said data transfer switch further comprises a plurality of buses.

14. An integrate multimedia system having a multimedia processor disposed in an integrated circuit, said system comprising:

a processor disposed within said multimedia processor for controlling the operation of said multimedia processor;

a data transfer switch disposed within said multimedia processor and coupled to said processor for transferring data to various modules of said multimedia processor, at least one of which is a data cache, wherein said data transfer switch is configured to transfer data in either direction between said data cache and a module within said multimedia processor as requested by said modules;

a data steamer coupled to said data transfer switch, and configured to schedule simultaneous data transfers among the various modules disposed within said multimedia processor, in accordance with corresponding channel allocations;

an interface unit coupled to said data streamer having a plurality of input/output (I/O) device driver units; and

a plurality of external I/O devices coupled to said plurality of I/O device driver units via a multiplexer.

15. The system in accordance with claim 14, wherein each one of said external I/O devices is controlled by a corresponding one of said T/O device driver units.

16. The system in accordance with claim 15, wherein one of said external I/O devices is an NTSC decoder.

17. The system in accordance with claim 15, wherein one of said external I/O devices is an NTSC encoder.

18. The system in accordance with claim 15, wherein one of said external I/O devices is a demodulator unit configured to demodulate wireless communications signals.

19. The system in accordance with claim 18, wherein said demodulator unit communicates with said multimedia processor in accordance with a transport channel interface arrangement.

20. The system in accordance with claim 15, wherein said multimedia processor provides video signals and three dimensional graphic signals to an external video display device.

21. The system in accordance with claim 15, wherein one of said external I/O devices is an ISDN interface.

22. The system in accordance with claim 15, wherein one of said external I/O devices is an audio coder and decoder (CODEC) unit.

23. The system in accordance with claim 14, wherein said data cache is directly coupled to said processor and said data transfer switch.

24. The system in accordance with claim 14, wherein said plurality of modules among which said data streamer configures to schedule simultaneous data transfers include the interface unit which is capable of controlling the external I/O devices, and a memory controller which is capable of controlling an external memory.

25. The system in accordance with claim 24, wherein said plurality of modules among which said data streamer configures to schedule simultaneous data transfers further include another interface unit which is capable of communicating with a first host processor.

26. The system in accordance with claim 14, wherein said data transfer switch further comprises a plurality of buses.