PCI express-compatible controller and interface for flash memory
First Claim
1. A method of performing an operation on a flash device, the operation being requested by a host separate from the flash device, the operation being PCI Express-compatible, the method comprising:
- sending a first memory request from the host to the flash device, wherein the first memory request includes a command word setting in a header,wherein the command word setting indicates the operation to be performed on the flash device, andwherein the first memory request further includes memory mapped I/O addresses in the header, the memory mapped I/O addresses comprising a command word port and a data value port.
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Accused Products
Abstract
A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.
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Citations
20 Claims
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1. A method of performing an operation on a flash device, the operation being requested by a host separate from the flash device, the operation being PCI Express-compatible, the method comprising:
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sending a first memory request from the host to the flash device, wherein the first memory request includes a command word setting in a header, wherein the command word setting indicates the operation to be performed on the flash device, and wherein the first memory request further includes memory mapped I/O addresses in the header, the memory mapped I/O addresses comprising a command word port and a data value port. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification