Processing system with dedicated local memories and busy identification
First Claim
1. A processing system, comprising:
- a processing unit; and
a plurality of sub-processing units for processing programs and data, each of the sub-processing units including a dedicated local memory for storing selected programs and data, the dedicated local memory including a plurality of addressable memory locations and a plurality of additional memory segments, each of the additional memory segments being directly associated with a respective one of the plurality of addressable memory locations and being operable to store a busy identifier therein, and at least one of the sub-processing units being operable to communicate with the processing unit;
wherein the dedicated local memory of each respective sub-processing unit is not a cache memory and does not support cache coherency, andwherein each busy identifier is employed by the processing system to synchronize data reading and writing between the respective addressable memory location and an external memory, each busy identifier identifying a first condition wherein the respective addressable memory location is usable for writing any data or a second condition wherein the respective addressable memory location is usable for writing only specific data retrievable from the external memory.
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Abstract
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system is provided for processing programs and data. The processing system has a processing unit and multiple sub-processing units. Each sub-processing unit includes a dedicated local memory for storing programs and data. The dedicated local memory of each respective sub-processing unit is not a cache memory. In an alternative, multiple computing devices may connect to one another via a communications network, and each computing device may include at least one processing element having the processing unit and sub-processing units.
87 Citations
16 Claims
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1. A processing system, comprising:
a processing unit; and a plurality of sub-processing units for processing programs and data, each of the sub-processing units including a dedicated local memory for storing selected programs and data, the dedicated local memory including a plurality of addressable memory locations and a plurality of additional memory segments, each of the additional memory segments being directly associated with a respective one of the plurality of addressable memory locations and being operable to store a busy identifier therein, and at least one of the sub-processing units being operable to communicate with the processing unit; wherein the dedicated local memory of each respective sub-processing unit is not a cache memory and does not support cache coherency, and wherein each busy identifier is employed by the processing system to synchronize data reading and writing between the respective addressable memory location and an external memory, each busy identifier identifying a first condition wherein the respective addressable memory location is usable for writing any data or a second condition wherein the respective addressable memory location is usable for writing only specific data retrievable from the external memory. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11, 12)
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2. A processing system, comprising:
a plurality of computing devices capable of connecting to one another via a communications network, each of the computing devices comprising at least one processing element, the at least one processing element comprising; a processing unit; and a plurality of sub-processing units for processing programs and data, each of the sub-processing units including a dedicated local memory for storing selected programs and data, the dedicated local memory including a plurality of addressable memory locations and a plurality of additional memory segments, each of the additional memory segments being directly associated with a respective one of the plurality of addressable memory locations and being operable to store a busy identifier therein, and at least one of the sub-processing units being operable to communicate with the processing unit; wherein the dedicated local memory of each respective sub-processing unit is not a cache memory and does not support cache coherency, and wherein each busy identifier is employed by the processing system to synchronize data reading and writing between the respective addressable memory location and an external memory, each busy identifier identifying a first condition wherein the respective addressable memory location is usable for writing any data or a second condition wherein the respective addressable memory location is usable for writing only specific data retrievable from the external memory. - View Dependent Claims (3, 13, 14, 15, 16)
Specification