High-voltage vertical transistor with a multi-gradient drain doping profile

• US 7,459,366 B2
• Filed: 12/19/2007
• Issued: 12/02/2008
• Est. Priority Date: 09/07/2001
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Banerjee, Sujit, Disney, Donald Ray
• Primary Examiner(s): Smoot; Stephen W
• Application Number:
  US12/004,166
• Publication Number:
  US 20080102581A1
• Time in Patent Office: 349 Days
• Field of Search: 438/454
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: Y10S 438/925 Fluid growth doping control, e.g. delta doping

Abstract

A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A method of fabricating high-voltage transistor comprising:

forming an epitaxial layer on a semiconductor substrate, the epitaxial layer and the semiconductor substrate being of a first conductivity type, the epitaxial layer being formed with first and second sections having respective first and second doping concentration gradients that differ by at least 10%, the first and second sections being formed below an upper surface of the epitaxial layer, the first section being formed above the second section, doping concentration in each of the first and second sections increasing with distance from the upper surface;

forming first and second trenches in the epitaxial layer that extend vertically from the upper surface to define a mesa, the first and second sections comprising a drift region of the mesa;

forming first and second field plate members in the first and second trenches, respectively, the first and second field plate members being formed of a conductive material fully insulated from the mesa by a dielectric material;

forming source and body regions in an upper portion of the mesa, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source from the first section of the drift region;

forming a gate embedded within the dielectric material adjacent the body region.

2. The method of claim 1 further comprising:

forming a source electrode connected to the source region and to the first and second field plates; and

forming a drain electrode connected to the substrate.

3. The method of claim 1 wherein the first conductivity type comprises n-type and the second conductivity type comprises p-type.

4. The method of claim 1 wherein the forming of first and second field plate members comprises:

forming a layer of the dielectric material in each of the first and second trenches, the layer partially filling each of the trenches and covering first and second sidewall portions of the first and second trenches, respectively; and

filling a remaining portion of the first and second trenches with the conductive material.

5. The method of claim 1 wherein the dielectric material comprises silicon dioxide.

6. The method of claim 1 wherein the conductive material comprises doped polysilicon.

7. A method of fabricating high-voltage transistor comprising:

forming an epitaxial layer with a doping concentration gradient that varies in a substantially continuous manner in a vertical direction through a lower portion of the epitaxial layer, the doping concentration gradient in the lower portion increasing with distance from an upper surface of the epitaxial layer, the doping concentration gradient differing by at least 10 % from near a top of the lower portion to near a bottom of the lower portion;

forming first and second trenches in the epitaxial layer that extend vertically from the upper surface to define a mesa, the lower portion comprising a drift region of the mesa;

forming first and second field plate members in the first and second trenches, respectively, the first and second field plate members being formed of a conductive material fully insulated from the mesa by a dielectric material.

8. The method of claim 7 wherein the epitaxial layer is formed with a first conductivity type.

9. The method of claim 8 further comprising:

forming source and body regions in an upper portion of the mesa, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source from the lower portion of the drift region.

10. The method of claim 7 further comprising:

forming a gate embedded within the dielectric material adjacent the body region.