Hot carrier injection programmable structure including discontinuous storage elements and spacer control gates in a trench and a method of using the same

• US 7,459,744 B2
• Filed: 09/22/2006
• Issued: 12/02/2008
• Est. Priority Date: 07/25/2005
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Hong, Cheong M., Li, Chi-Nan
• Primary Examiner(s): Tran, Long K
• Application Number:
  US11/525,747
• Publication Number:
  US 20070020851A1
• Time in Patent Office: 802 Days
• Field of Search: 257/E29.26, 257/E29.257, 257/302, 257/E29.201, 257/330, 257/156, 257/242, 257/259, 365/185.18, 438/156, 438/158, 438/206, 438/212, 438/268, 438/259, 438/270, 438/271, 438/589
• US Class Current: 257/302
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A programmable storage device includes a first diffusion region underlying a portion of a first trench defined in a semiconductor substrate and a second diffusion region occupying an upper portion of the substrate adjacent to the first trench. The device includes a charge storage stack lining sidewalls and a portion of a floor of the first trench. The charge storage stack includes a layer of discontinuous storage elements (DSEs). Electrically conductive spacers formed on opposing sidewalls of the first trench adjacent to respective charge storage stacks serve as control gates for the device. The DSEs may be silicon, polysilicon, metal, silicon nitride, or metal nitride nanocrystals or nanoclusters. The storage stack includes a top dielectric of CVD silicon oxide overlying the nanocrystals overlying a bottom dielectric of thermally formed silicon dioxide. The device includes first and second injection regions in the layer of DSEs proximal to the first and second diffusion regions.

Claims

1. An array of storage cells wherein at least one of the storage cells comprises:

a semiconductor substrate including an uppermost surface and a first trench extending from the uppermost surface;

a first diffusion region underlying a portion of a first trench defined in the semiconductor substrate wherein a conductivity type of the first diffusion region is opposite a conductivity type of the semiconductor substrate;

a second diffusion region occupying an upper portion of the semiconductor substrate adjacent to the first trench wherein a conductivity type of the second diffusion region is opposite the conductivity type of the semiconductor substrate;

a charge storage stack lining sidewalls and a portion of a floor of the first trench wherein the charge storage stack includes a layer of discontinuous storage elements (DSEs); and

electrically conductive spacers formed on sidewalls of the first trench adjacent to respective charge storage stacks, wherein substantially all of the electrically conductive spacers lie at elevations between an uppermost surface of the semiconductor substrate and a bottom of the trench.

2. The storage array of claim 1, wherein the DSEs include silicon nanocrystals.

3. The storage array of claim 1, wherein the spacers define a gap overlying the first diffusion region.

4. The storage array of claim 1, wherein the storage cell includes a first injection region within the layer of DSEs proximal to the second diffusion region and a second injection within the layer of DSEs proximal to the first diffusion region.

5. The storage array of claim 4, further comprising a second trench adjacent to the second diffusion region, charge storage stacks lining sidewalls of the second trench and conductive gate spacers adjacent to the charge storage stacks in the second trench and still farther comprising a diffusion region underlying a gap defined between the spacers in the second trench.

6. The storage array of claim 1, wherein the DSEs include DSEs underlying the conductive spacers.

7. The array of claim 1, wherein each storage cell includes a plurality of the DSEs.

8. The array of claim 1, wherein the electrically conductive spacers are control gates for the storage cells.

9. The array of claim 8, wherein within the first trench, the control gates are spaced apart from a center of the first trench.

10. The array of claim 1, wherein the second diffusion region lies at a wall of the first trench.

11. The array of claim 1, wherein all of the layer of the DSE lies at an elevation below an uppermost surface of the semiconductor substrate.

12. The array of claim 1, further comprising a plug lying within a center of the first trench, wherein the plug comprises a conductive center that contacts the first diffusion region.

13. The array of claim 1, wherein the electrically conductive spacers comprise polysilicon.

14. The array of claim 1, wherein the electrically conductive spacers comprise a metal material.

15. The array of claim 1, wherein the DSEs are silicon nanocrystals.

16. The array of claim 1, wherein the DSEs comprise a nitride.

17. The array of claim 1, wherein the DSEs comprise silicon nitride.

18. The array of claim 1, wherein the electrically conductive spacers are spaced apart from the DSEs.

19. The array of claim 18, further comprising a dielectric layer lying between the electrically conductive spacers and the DSEs.

20. The array of claim 1, further comprising a dielectric layer lying between the DSEs and a wall and a bottom of the first trench.