Post passivation interconnection schemes on top of the IC chips
First Claim
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1. A chip structure comprising:
- a silicon substrate;
a first repeater in and on said silicon substrate;
a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first interconnecting structure connected to said first repeater, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a dielectric body over said silicon substrate, wherein said first interconnecting structure is in said dielectric body, and wherein said dielectric body comprises a dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said dielectric body, wherein said passivation layer comprises a nitride layer;
a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; and
a second metallization structure over said passivation layer and over said first via, wherein said second metallization structure is connected to said first repeater through, in sequence, said first via and said first interconnecting structure.
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Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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Citations
28 Claims
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1. A chip structure comprising:
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a silicon substrate; a first repeater in and on said silicon substrate; a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first interconnecting structure connected to said first repeater, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric body over said silicon substrate, wherein said first interconnecting structure is in said dielectric body, and wherein said dielectric body comprises a dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said dielectric body, wherein said passivation layer comprises a nitride layer; a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; and a second metallization structure over said passivation layer and over said first via, wherein said second metallization structure is connected to said first repeater through, in sequence, said first via and said first interconnecting structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 23, 24, 27)
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12. A chip structure comprising:
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a silicon substrate; a first transceiver in and on said silicon substrate; a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first interconnecting structure connected to said first transceiver, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric body over said silicon substrate, wherein said first interconnecting structure is in said dielectric body, and wherein said dielectric body comprises a dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said dielectric body, wherein said passivation layer comprises a nitride layer; a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; and a second metallization structure over said passivation layer and over said first via, wherein said second metallization structure is connected to said first transceiver through, in sequence, said first via and said first interconnecting structure. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 25, 26, 28)
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Specification