Post passivation interconnection schemes on top of the IC chips

• US 7,459,790 B2
• Filed: 04/19/2007
• Issued: 12/02/2008
• Est. Priority Date: 10/15/2003
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Picardat; Kevin M
• Application Number:
  US11/788,221
• Publication Number:
  US 20070200244A1
• Time in Patent Office: 593 Days
• Field of Search: 257/690, 257/700, 257/691, 257/773, 257/774, 257/E21.575, 438614-616, 438/622, 438/631, 438/637, 438/638, 438/107, 438/110, 438/624
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 Nitrogen [N]
• CPC Class Codes: H01L 2924/01011 Sodium [Na]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A chip structure comprising:

a silicon substrate;

a first repeater in and on said silicon substrate;

a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first interconnecting structure connected to said first repeater, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric body over said silicon substrate, wherein said first interconnecting structure is in said dielectric body, and wherein said dielectric body comprises a dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure and over said dielectric body, wherein said passivation layer comprises a nitride layer;

a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; and

a second metallization structure over said passivation layer and over said first via, wherein said second metallization structure is connected to said first repeater through, in sequence, said first via and said first interconnecting structure.

2. The chip structure of claim 1, wherein said nitride layer has a thickness greater than 0.4 micrometers.

3. The chip structure of claim 1 further comprising a polymer layer between said passivation layer and said second metallization structure, wherein said polymer layer has a thickness between 2 and 150 micrometers.

4. The chip structure of claim 3, wherein said polymer layer comprises polyimide.

5. The chip structure of claim 3 further comprising a polymer layer over said second metallization structure, wherein said polymer layer has a thickness between 2 and 150 micrometers.

6. The chip structure of claim 5, wherein said polymer layer comprises polyimide.

7. The chip structure of claim 1 further comprising a second repeater in and on said silicon substrate and a second via in said passivation layer, wherein said first metallization structure further comprises a second interconnecting structure over said silicon substrate and in said dielectric body, wherein said second interconnecting structure is connected to said second repeater and to said second via, and wherein said first repeater is connected to said second repeater through, in sequence, said first interconnecting structure, said first via, said second metallization structure, said second via and said second interconnecting structure.

8. The chip structure of claim 1, wherein said second metallization structure comprises electroplated copper.

9. The chip structure of claim 1, wherein said second metallization structure comprises electroplated gold.

10. The chip structure of claim 1, wherein said second metallization structure comprises an electroplated metal.

11. The chip structure of claim 1, wherein said first repeater comprises a driver and a receiver connected to said driver.

23. The chip structure of claim 3, wherein said polymer layer comprises benzocyclobutene (BCB).

24. The chip structure of claim 5, wherein said polymer layer comprises benzocyclobutene (BCB).

27. The chip structure of claim 1, wherein said passivation layer further comprises an oxide layer.

12. A chip structure comprising:

a silicon substrate;

a first transceiver in and on said silicon substrate;

a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first interconnecting structure connected to said first transceiver, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric body over said silicon substrate, wherein said first interconnecting structure is in said dielectric body, and wherein said dielectric body comprises a dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure and over said dielectric body, wherein said passivation layer comprises a nitride layer;

a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; and

a second metallization structure over said passivation layer and over said first via, wherein said second metallization structure is connected to said first transceiver through, in sequence, said first via and said first interconnecting structure.

13. The chip structure of claim 12, wherein said nitride layer has a thickness greater than 0.4 micrometers.

14. The chip structure of claim 12 further comprising a polymer layer between said passivation layer and said second metallization structure, wherein said polymer layer has a thickness between 2 and 150 micrometers.

15. The chip structure of claim 14, wherein said polymer layer comprises polyimide.

16. The chip structure of claim 14 further comprising a polymer layer over said second metallization structure, wherein said polymer layer has a thickness between 2 and 150 micrometers.

17. The chip structure of claim 16, wherein said polymer layer comprises polyimide.

18. The chip structure of claim 12 further comprising a second transceiver in and on said silicon substrate and a second via in said passivation layer, wherein said first metallization structure further comprises a second interconnecting structure over said silicon substrate and in said dielectric body, wherein said second interconnecting structure is connected to said second transceiver and to said second via, and wherein said first transceiver is connected to said second transceiver through, in sequence, said first interconnecting structure, said first via, said second metallization structure, said second via and said second interconnecting structure.

19. The chip structure of claim 12, wherein said second metallization structure comprises electroplated copper.

20. The chip structure of claim 12, wherein said second metallization structure comprises electroplated gold.

21. The chip structure of claim 12, wherein said second metallization structure comprises an electroplated metal.

22. The chip structure of claim 12, wherein said first transceiver comprises a driver and a receiver connected to said driver.

25. The chip structure of claim 14, wherein said polymer layer comprises benzocyclobutene (BCB).

26. The chip structure of claim 16, wherein said polymer layer comprises benzocyclobutene (BCB).

28. The chip structure of claim 12, wherein said passivation layer further comprises an oxide layer.