Post passivation interconnection schemes on top of IC chip
First Claim
Patent Images
1. A chip comprising:
- a silicon substrate;
a first internal circuit in or on said silicon substrate;
an ESD circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit;
a first via in said dielectric layer and directly over said first internal circuit, wherein said first via is connected to said first internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;
a second via in said passivation layer, wherein said second via is connected to said first interconnecting structure;
a third via in said passivation layer and directly over said first via, wherein said third via is connected to said first via; and
a second interconnecting structure over said passivation layer and over said second and third vias, wherein said second interconnecting structure is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said third via and said first via.
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Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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Citations
20 Claims
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1. A chip comprising:
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a silicon substrate; a first internal circuit in or on said silicon substrate; an ESD circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit; a first via in said dielectric layer and directly over said first internal circuit, wherein said first via is connected to said first internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride; a second via in said passivation layer, wherein said second via is connected to said first interconnecting structure; a third via in said passivation layer and directly over said first via, wherein said third via is connected to said first via; and a second interconnecting structure over said passivation layer and over said second and third vias, wherein said second interconnecting structure is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said third via and said first via. - View Dependent Claims (2, 3, 4, 5)
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6. A chip comprising:
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a silicon substrate; a first internal circuit in or on said silicon substrate; an ESD circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit; a first via in said dielectric layer and directly over said first internal circuit, wherein said first via is connected to said first internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride; a polymer layer over said passivation layer; a second via in said polymer layer, wherein said second via is connected to said first interconnecting structure; a third via in said polymer layer and directly over said first via, wherein said third via is connected to said first via; and a second interconnecting structure in said polymer layer and over said passivation layer, wherein said second interconnecting structure is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said third via and said first via. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A chip comprising:
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a silicon substrate; a first internal circuit in or on said silicon substrate; an ESD circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride; a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; a third interconnecting structure over said passivation layer and over said first and second vias, wherein said third interconnecting structure is connected to said first and second vias, wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, and wherein said ESD circuit is connected, in parallel with said first internal circuit, to an external connection point of said third interconnecting structure; and a polymer over said third interconnecting structure and over said passivation layer. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification