Digital calibration circuits, devices and systems including same, and methods of operation
First Claim
1. A calibration circuit comprising:
- a driver circuit having a plurality of calibration transistors configured to receive a plurality of adjustment signals, the driver circuit operable to generate a first output signal having a value corresponding to the plurality of adjustment signals;
a comparator circuit coupled to the driver circuit to receive the first output signal, the comparator circuit operable to generate a first control signal determined by the difference between the value of the first output signal and a predetermined value, and the comparator circuit further operable to generate a second control signal determined by whether the first output signal is greater than the predetermined value, the comparator circuit comprising;
a first comparator configured to compare the first output signal to a value above the predetermined value;
a second comparator configured to compare the first output signal to a value below the predetermined value; and
a third comparator configured to compare the first output signal to the predetermined value; and
a binary searcher coupled to receive the first and second control signals from the comparator circuit, and operable to select either a relatively larger binary step count or a relatively smaller binary step count in response to the first control signal and determine the upwards or downwards direction of the selected binary step count in response to the second control signal, the binary searcher further operable to adjust the plurality of calibration transistors in accordance with the selected binary step count and in the selected direction of the count.
8 Assignments
0 Petitions
Accused Products
Abstract
A calibration circuit for matching the output impedance of a driver by calibrating adjustments to the driver is described. The calibration circuit includes a driver circuit with a plurality of calibration transistors configured to receive a plurality of adjustment signals. The calibration circuit also includes a comparator circuit, and a binary searcher. The driver provides a signal corresponding to an output impedance to the comparator circuit. The output impedance signal is compared to a target impedance, and the comparator circuit then provides logic signals to the binary searcher representing whether the output impedance is greater than the target impedance. The binary searcher then selects a type of step size and count direction, in response to the logic signals, to count the number of steps for adjusting the calibration transistors of the driver.
96 Citations
51 Claims
-
1. A calibration circuit comprising:
-
a driver circuit having a plurality of calibration transistors configured to receive a plurality of adjustment signals, the driver circuit operable to generate a first output signal having a value corresponding to the plurality of adjustment signals; a comparator circuit coupled to the driver circuit to receive the first output signal, the comparator circuit operable to generate a first control signal determined by the difference between the value of the first output signal and a predetermined value, and the comparator circuit further operable to generate a second control signal determined by whether the first output signal is greater than the predetermined value, the comparator circuit comprising; a first comparator configured to compare the first output signal to a value above the predetermined value; a second comparator configured to compare the first output signal to a value below the predetermined value; and a third comparator configured to compare the first output signal to the predetermined value; and a binary searcher coupled to receive the first and second control signals from the comparator circuit, and operable to select either a relatively larger binary step count or a relatively smaller binary step count in response to the first control signal and determine the upwards or downwards direction of the selected binary step count in response to the second control signal, the binary searcher further operable to adjust the plurality of calibration transistors in accordance with the selected binary step count and in the selected direction of the count. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. An output driver impedance calibration circuit comprising:
-
a driver having a plurality of transistors, the driver configured to receive a plurality of adjustment signals, the driver being operable to select a subset of transistors in response to the plurality of adjustment signals and to generate a signal corresponding to an adjusted output impedance based on the subset of transistors that are selected; a comparator circuit configured to receive the signal corresponding to the adjusted output impedance and a signal corresponding to a target impedance, the comparator circuit operable to compare the received driver and target impedance signals to generate a set of logic signals from which the difference in magnitude between the adjusted output impedance and the target impedance can be determined; a filtering circuit coupled to receive the set of logic signals from the comparator circuit, and operable to generate a first adjustment control signal indicative of whether the difference between the adjusted output impedance and the target impedance is greater than a predetermined value, and further operable to generate a second adjustment control signal indicative of whether the output impedance is greater than the target impedance; and a binary searcher coupled to receive the first and second adjustment control signals, and operable to select either a relatively larger adjustment step size or a relatively smaller adjustment step size in response to the first adjustment control signal and operable to select a step count in the upward or downward direction in response to the second adjustment control signal, the binary searcher further operable to provide the plurality of adjustment signals to the driver in accordance with the selected adjustment step size and step count. - View Dependent Claims (11, 12, 13, 14, 15)
-
-
16. A memory device, comprising:
-
an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the control bus; an array of memory cells coupled to the address decoder, control circuit, and read/write circuit; an output driver circuit for outputting data read from the array of memory cells; and a calibration circuit for a driver comprising; a driver circuit having a plurality of calibration transistors configured to receive a plurality of adjustment signals, the driver circuit operable to generate a first output signal having a value corresponding to the plurality of adjustment signals; a comparator circuit coupled to the driver circuit to receive the first output signal, the comparator circuit operable to generate a first control signal determined by the difference between the value of the first output signal and a predetermined value, and the comparator circuit further operable to generate a second control signal determined by whether the first output signal is greater than the predetermined value, the comparator circuit comprising; a first comparator configured to compare the first output signal to a value above the predetermined value; a second comparator configured to compare the first output signal to a value below the predetermined value; and a third comparator configured to compare the first output signal to the predetermined value; and a binary searcher coupled to receive the first and second control signals from the comparator circuit, and operable to select either a relatively larger binary step count or a relatively smaller binary step count in response to the first control signal and determine the upwards or downwards direction of the selected binary step count in response to the second control signal, the binary searcher further operable to adjust the plurality of calibration transistors in accordance with the selected binary step count and in the selected direction of the count. - View Dependent Claims (17, 18, 19, 20, 21)
-
-
22. A memory device, comprising:
-
an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the control bus; an array of memory cells coupled to the address decoder, control circuit, and read/write circuit; an output driver circuit for outputting data read from the array of memory cells; and an output driver impedance calibration circuit comprising; a driver having a plurality of transistors, the driver configured to receive a plurality of adjustment signals, the driver being operable to select a subset of transistors in response to the plurality of adjustment signals and generate a signal corresponding to an adjusted output impedance based on the subset of transistors that are selected; a comparator circuit configured to receive the signal corresponding to the adjusted output impedance and a signal corresponding to a target impedance, the comparator circuit operable to compare the received driver and target impedance signals to generate a set of logic signals from which the difference in magnitude between the adjusted output impedance and the target impedance can be determined; a filtering circuit coupled to receive the set of logic signals from the comparator circuit, and operable to generate a first adjustment control signal indicative of whether the difference between the adjusted output impedance and the target impedance is greater than a predetermined value, and further operable to generate a second adjustment control signal indicative of whether the output impedance is greater than the target impedance; and a binary searcher coupled to receive the first and second adjustment control signals, and operable to select either a relatively larger adjustment step size or a relatively smaller adjustment step size in response to the first adjustment control signal and operable to select a step count in the upward or downward direction in response to the second adjustment control signal, the binary searcher further operable to provide the plurality of adjustment signals to the driver in accordance with the selected adjustment step size and step count. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
-
-
30. A computer system, comprising:
-
a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device coupled to the processor, the memory device comprising; an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the control bus; an array of memory cells coupled to the address decoder, control circuit, and read/write circuit; an output driver circuit for outputting data read from the array of memory cells; and a calibration circuit for a driver comprising; a driver circuit having a plurality of calibration transistors configured to receive a plurality of adjustment signals, the driver circuit operable to generate a first output signal having a value corresponding to the plurality of adjustment signals; a comparator circuit coupled to the driver circuit to receive the first output signal, the comparator circuit operable to generate a first control signal determined by the difference between the value of the first output signal and a predetermined value, and the comparator circuit further operable to generate a second control signal determined by whether the first output signal is greater than the predetermined value, the comparator circuit comprising; a first comparator configured to compare the first output signal to a value above the predetermined value; a second comparator configured to compare the first output signal to a value below the predetermined value; and a third comparator configured to compare the first output signal to the predetermined value; and a binary searcher coupled to receive the first and second control signals from the comparator circuit, and operable to select either a relatively larger binary step count or a relatively smaller binary step count in response to the first control signal and determine the upwards or downwards direction of the selected binary step count in response to the second control signal, the binary searcher further operable to adjust the plurality of calibration transistors in accordance with the selected binary step count and in the selected direction of the count. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37)
-
-
38. A computer system, comprising:
-
a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device coupled to the processor, the memory device comprising; an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the control bus; an array of memory cells coupled to the address decoder, control circuit, and read/write circuit; an output driver circuit for outputting data read from the array of memory cells; and an output driver impedance calibration circuit comprising; a driver having a plurality of transistors, the driver configured to receive a plurality of adjustment signals, the driver being operable to select a subset of transistors in response to the plurality of adjustment signals and generate a signal corresponding to an adjusted output impedance based on the subset of transistors that are selected; a comparator circuit configured to receive the signal corresponding to the adjusted output impedance and a signal corresponding to a target impedance, the comparator circuit operable to compare the received driver and target impedance signals to generate a set of logic signals from which the difference in magnitude between the adjusted output impedance and the target impedance can be determined; a filtering circuit coupled to receive the set of logic signals from the comparator circuit, and operable to generate a first adjustment control signal indicative of whether the difference between the adjusted output impedance and the target impedance is greater than a predetermined value, and further operable to generate a second adjustment control signal indicative of whether the output impedance is greater than the target impedance; and a binary searcher coupled to receive the first and second adjustment control signals, and operable to select either a relatively larger adjustment step size or a relatively smaller adjustment step size in response to the first adjustment control signal and operable to select a step count in the upward or downward direction in response to the second adjustment control signal, the binary searcher further operable to provide the plurality of adjustment signals to the driver in accordance with the selected adjustment step size and step count. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45)
-
-
46. A method for calibrating a driver, the method comprising:
-
comparing the output impedance of the driver to a target output impedance to determine if the output impedance is within a first range of the target output impedance or a second range of the target output impedance; adjusting the output impedance of the driver in binary steps if the output impedance is within a first range of the target output impedance; filtering the output impedance of the driver if the output impedance of the driver to a target output impedance is within as second range of the target output impedance; adjusting the output impedance of the driver in binary substeps if the output impedance is within a second range of the target output impedance; repeating at least one comparison and adjustment of the output impedance of the driver to a target output impedance; and outputting a final impedance of the driver based on the at least one comparison. - View Dependent Claims (47, 48, 49, 50, 51)
-
Specification