Apparatus for receiver equalization

• US 7,459,980 B2
• Filed: 06/04/2007
• Issued: 12/02/2008
• Est. Priority Date: 06/27/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Drottar, Ken
• Primary Examiner(s): Nguyen; Khanh V
• Application Number:
  US11/757,806
• Publication Number:
  US 20070247228A1
• Time in Patent Office: 547 Days
• Field of Search: 330/82, 330/253, 330/260, 330/277, 330/280, 330/291, 330/293, 330/304
• US Class Current: 330/304
• CPC Class Codes: H03F 1/086 with FET's
• CPC Class Codes: H03F 1/34 Negative-feedback-circuit arrangements with or without positive feedback H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence ; for rejection of common mode signals H03F3/45479
• CPC Class Codes: H03F 1/342 in field-effect transistor amplifiers
• CPC Class Codes: H03F 1/42 Modifications of amplifiers to extend the bandwidth
• CPC Class Codes: H03F 2200/36 the amplifier comprising means for increasing the bandwidth
• CPC Class Codes: H03F 3/16 with field-effect devices
• CPC Class Codes: H03F 3/45237 Complementary long tailed pairs having parallel inputs and being supplied in series
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

In some embodiments an apparatus includes an amplifier, a first inverter having an input coupled to an output of the amplifier, and a second inverter having an input coupled to an output of the first inverter and an output, where the output of the second inverter is fed back to an input of the amplifier. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

an amplifier; and

a delay and gain circuit coupled to an output of the amplifier, wherein an output of the delay and gain circuit is fed back to the amplifier;

wherein the amplifier provides positive feedback and the output of the delay and gain circuit is fed back to the amplifier as negative feedback; and

wherein the amplifier mixes the positive feedback and the negative feedback.

2. The apparatus as claimed in claim 1, wherein the amplifier is a CMOS amplifier.

3. The apparatus as claimed in claim 2, wherein the CMOS amplifier is a hybrid Bazes and Chappell amplifier.

4. The apparatus as claimed in claim 3, wherein:

the amplifier includes a first, a second and a third pMOS transistor and a first, a second and a third nMOS transistor;

a gate of the first pMOS transistor and a gate of the first nMOS transistor are coupled to an input;

a gate of the second pMOS transistor and a gate of the second nMOS transistor are coupled to a drain of the first pMOS transistor and a drain of the first nMOS transistor; and

a gate of the third pMOS transistor and a gate of the third nMOS transistor are coupled to an inverse input.

5. The apparatus as claimed in claim 4, wherein the gate of the second pMOS transistor and the gate of the second nMOS transistor are coupled to the drain of the first pMOS transistor and the drain of the first nMOS transistor via a resistor.

6. The apparatus as claimed in claim 1, wherein the delay and gain circuit includes a first inverter and a second inverter.

7. The apparatus as claimed in claim 6, wherein the second inverter is approximately four times the size of the first inverter.

8. The apparatus as claimed in claim 6, wherein the first inverter is approximately one-fourth the size of the output of the amplifier.

9. The apparatus as claimed in claim 6, wherein the first inverter is approximately one-fourth the size of the output of the amplifier and the first inverter is approximately one-fourth the size of the second inverter.

10. The apparatus as claimed in claim 1, wherein the amplifier further includes a resistor.

11. The apparatus as claimed in claim 6, wherein the amplifier further includes a resistor.

12. The apparatus as claimed in claim 1, wherein the amplifier further includes a resistor that mixes the positive feedback and the negative feedback.

13. The apparatus as claimed in claim 6, wherein the amplifier further includes a resistor that mixes the positive feedback and the negative feedback

14. The apparatus as claimed in claim 4, wherein the amplifier further includes a resistor, wherein the resistor is included in a circuit that mixes positive feedback provided by the amplifier and negative feedback provided to the amplifier from the output of the second inverter.

15. The apparatus as claimed in claim 6, wherein the amplifier further includes a resistor, wherein the resistor is included in a circuit that mixes positive feedback provided by the amplifier and negative feedback provided to the amplifier from the output of the second inverter.

16. The apparatus as claimed in claim 1, further comprising an output, wherein the output is coupled to the output of the second inverter.

17. The apparatus as claimed in claim 16, wherein the output does not include evidence of precharging from the amplifier.

18. The apparatus as claimed in claim 6, further comprising an output, wherein the output is coupled to the output of the second inverter.

19. The apparatus as claimed in claim 18, wherein the output does not include evidence of precharging from the amplifier.

20. The apparatus as claimed in claim 1, wherein the amplifier includes a resistor, and wherein the resistor is included in a circuit that mixes the positive feedback and the negative feedback.

21. The apparatus as claimed in claim 1, the amplifier further comprising:

an inverse input;

a first pMOS transistor having a gate coupled to the input of the amplifier;

a second pMOS transistor;

a third pMOS transistor having a gate coupled to the inverse input of the amplifier and having a source coupled to a source of the first pMOS transistor and to a drain of the second pMOS transistor;

a first nMOS transistor having a gate coupled to the input of the amplifier;

a second nMOS transistor having a gate coupled to a drain of the first pMOS transistor, a drain of the first nMOS transistor, and to a gate of the second pMOS transistor; and

a third nMOS transistor having a gate coupled to the inverse input of the amplifier, a drain coupled to a drain of the third pMOS transistor and a source coupled to a source of the first nMOS transistor and to a drain of the second nMOS transistor, wherein the output of the amplifier is coupled to the drain of the third pMOS transistor and to the drain of the third nMOS transistor.

22. The apparatus as claimed in claim 21, the amplifier further comprising a resistor, wherein the gate of the second nMOS transistor and the gate of the second pMOS transistor are coupled directly together, and the drain of the first pMOS transistor and the drain of the first nMOS transistor are coupled directly together, wherein the direct coupling of the gate of the second nMOS transistor and the gate of the second pMOS transistor are coupled via the resistor to the direct coupling of the drain of the first pMOS transistor and the drain of the first nMOS transistor.

23. The apparatus according to claim 22, wherein the resistor has a resistance of approximately 5000 ohms.

24. The apparatus according to claim 21, the amplifier further comprising a control input, wherein the gate of the second nMOS transistor and the gate of the second pMOS transistor are coupled to the control input.

25. The apparatus according to claim 21, wherein a width of each of the first pMOS transistor, the second pMOS transistor and the third pMOS transistor is approximately 9.2 um, and wherein a width of the first nMOS transistor, the second nMOS transistor and the third nMOS transistor is approximately 4 um.

26. The apparatus according to claim 25, wherein a length of each of the first pMOS transistor, the second pMOS transistor, the third pMOS transistor, the first nMOS transistor, the second nMOS transistor and the third nMOS transistor is approximately 80 nm.