Low cost high density rectifier matrix memory

• US 7,460,384 B2
• Filed: 09/19/2005
• Issued: 12/02/2008
• Est. Priority Date: 06/22/2000
• Status: Expired due to Fees

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Contour Semiconductor, Inc.
• Inventors: Shepard, Daniel Robert
• Primary Examiner(s): Luu, Pho M.
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US11/229,941
• Publication Number:
  US 20060013029A1
• Time in Patent Office: 1,170 Days
• Field of Search: 365/100, 365/51, 365/201
• US Class Current: 365/51
• CPC Class Codes: G06K 5/04 Verifying the alignment of markings
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 63/10 Phase change RAM [PCRAM, PRAM] devices

Abstract

A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.

Claims

1. An electronic array circuit comprising:

a plurality of generally parallel rows and a plurality of generally parallel columns that are generally orthogonal and overlapping;

test circuitry comprising connections between the alternate ends of every evenly numbered row such that continuity of half of the rows can be tested by passing a current;

test circuitry further comprising connections between the alternate ends of every oddly numbered row such that continuity of the other half of the rows can be tested by passing a current.

2. The array circuit of claim 1 comprising:

test circuitry comprising connections between the alternate ends of every evenly numbered column such that continuity of half of the columns can be tested by passing a current;

test circuitry further comprising connections between the alternate ends of every oddly numbered column such that continuity of the other half of the columns can be tested by passing a current.

3. The array circuit of claim 2 comprising testing means for detecting a short-circuit between the evenly numbered columns and the oddly numbered columns.

4. The array circuit of claim 2 comprising testing means for detecting a short-circuit between the rows and the columns.

5. The array circuit of claim 1 comprising testing means for detecting a short-circuit between the evenly numbered rows and the oddly numbered rows.

6. The array circuit of claim 1 wherein each row exists on a different layer of a multilayered, three-dimensional array.