Semiconductor device

• US 7,460,396 B2
• Filed: 09/07/2006
• Issued: 12/02/2008
• Est. Priority Date: 09/13/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Shiba, Kazuyoshi, Oka, Yasushi
• Primary Examiner(s): Elms; Richard
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US11/470,651
• Publication Number:
  US 20070058441A1
• Time in Patent Office: 817 Days
• Field of Search: 365/185.28, 365/185.01, 365/185.05, 365/185.26, 257/315, 257/316
• US Class Current: 365/185.01
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a first main surface and, on the back side thereof, a second main surface;

a main circuit formation region placed over the first main surface of the semiconductor substrate; and

a nonvolatile memory region placed over the first main surface of the semiconductor substrate,

the nonvolatile memory region being equipped with;

a first well having a first conductivity type and formed over the main surface of the semiconductor substrate;

a second well having a second conductivity type, which type is opposite to the first conductivity type, and placed to be enclosed in the first well;

a third well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well, and to be enclosed in the first well;

a fourth well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well and the third well, and to be enclosed in the first well; and

a nonvolatile memory cell placed to two-dimensionally overlap with the second well, the third well and the fourth well,

the nonvolatile memory cell being equipped with;

a floating gate electrode placed to extend in a first direction so as to two-dimensionally overlap with the second well, the third well and the fourth well;

an element for programming and erasing data formed at a first position where the floating gate electrode two-dimensionally overlaps with the second well;

a field effect transistor for reading data formed at a second position where the floating gate electrode two-dimensionally overlaps with the third well; and

a capacitor element formed at a third position where the floating gate electrode two-dimensionally overlaps with the fourth well,

the element for programming and erasing data being equipped with;

a first electrode formed at the first position of the floating gate electrode;

a first insulating film formed between the first electrode and the semiconductor substrate;

a pair of second-conductivity type semiconductor regions formed in the second well at a position where the first electrode is sandwiched therebetween; and

the second well,

the field effect transistor for reading data being equipped with;

a second electrode formed at the second position of the floating gate electrode;

a second insulating film formed between the second electrode and the semiconductor substrate; and

a pair of first-conductivity-type semiconductor regions formed in the third well at a position where the second electrode is sandwiched therebetween, and

the capacitor element being equipped with;

a third electrode formed at the third position of the floating gate electrode;

a third insulating film formed between the third electrode and the semiconductor substrate;

a pair of second-conductivity-type semiconductor regions formed in the fourth well at a position where the third electrode is sandwiched therebetween; and

the fourth well.

2. A semiconductor device according to claim 1, wherein rewriting of data at the element for programming and erasing data is effected by means of an FN tunneling current of an entire channel surface.

3. A semiconductor device according to claim 1, wherein an external power supply fed from the outside of the semiconductor substrate is a single power supply.

4. A semiconductor device according to claim 1, wherein the length of the third electrode in a second direction, which crosses the first direction, is longer than the length of the first electrode and the second electrode in the second direction.

5. A semiconductor device according to claim 1, wherein the thickness of the first insulating film of the element for programming and erasing data is 10 nm or greater but not greater than 20 nm.

6. A semiconductor device according to claim 1,

wherein a low-breakdown-voltage field effect transistor driven at a first operating voltage and a high-breakdown-voltage field effect transistor driven at a second operating voltage higher than the first operating voltage are placed in the main circuit formation region, and

wherein a gate insulating film of the low-breakdown-voltage field effect transistor has a film thickness equal to that of the first insulating film.

7. A semiconductor device according to claim 1, wherein a select field effect transistor is electrically connected to the data-reading field effect transistor of the nonvolatile memory cell so as to be able to select the nonvolatile memory cell.

8. A semiconductor device, comprising:

a semiconductor substrate having a first main surface and, on the back side thereof, a second main surface;

a main circuit formation region placed over the first main surface of the semiconductor substrate; and

a nonvolatile memory region placed over the first main surface of the semiconductor substrate,

the nonvolatile memory region being equipped with;

a first well having a first conductivity type and formed over the main surface of the semiconductor substrate;

a second well having a second conductivity type, which type is opposite to the first conductivity type, and placed to be enclosed in the first well;

a third well having the second conductivity type, which type is opposite to the first conductivity type, and placed to extend along the second well while being electrically separated from the second well, and to be enclosed in the first well;

a fourth well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well and the third well, and to be enclosed in the first well; and

a plurality of nonvolatile memory cells placed to two-dimensionally overlap with the second well, the third well and the fourth well,

the plurality of nonvolatile memory cells each being equipped with;

a floating gate electrode placed to extend in a first direction so as to two-dimensionally overlap with the second well, the third well and the fourth well;

an element for programming and erasing data formed at a first position where the floating gate electrode two-dimensionally overlaps with the second well;

a field effect transistor for reading data formed at a second position where the floating gate electrode two-dimensionally overlaps with the third well; and

a capacitor element formed at a third position where the floating gate electrode two-dimensionally overlaps with the fourth well,

the element for programming and erasing data being equipped with;

a first electrode formed at the first position of the floating gate electrode;

a first insulating film formed between the first electrode and the semiconductor substrate;

a pair of second-conductivity type semiconductor regions formed in the second well at a position where the first electrode is sandwiched therebetween; and

the second well,

the field effect transistor for reading data being equipped with;

a second electrode formed at the second position of the floating gate electrode;

a second insulating film formed between the second electrode and the semiconductor substrate; and

a pair of first-conductivity-type semiconductor regions formed in the third well at a position where the second electrode is sandwiched therebetween, and

the capacitor element being equipped with;

a third electrode formed at the third position of the floating gate electrode;

a third insulating film formed between the third electrode and the semiconductor substrate;

a pair of second-conductivity-type semiconductor regions formed in the fourth well at a position where the third electrode is sandwiched therebetween; and

the fourth well.

9. A semiconductor device according to claim 8, wherein a select field effect transistor is electrically connected to the data reading field effect transistor of each of the plurality of nonvolatile memory cells so as to be able to select the each of the plurality of nonvolatile memory cells.

10. A semiconductor device, comprising:

a semiconductor substrate having a first main surface and, on the back side thereof, a second main surface;

a main circuit formation region placed over the first main surface of the semiconductor substrate; and

a nonvolatile memory region placed over the first main surface of the semiconductor substrate,

the nonvolatile memory region being equipped with;

a first well having a first conductivity type and formed over the main surface of the semiconductor substrate;

a second well having a second conductivity type, which type is opposite to the first conductivity type, and placed to be enclosed in the first well;

a third well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well, and to be enclosed in the first well;

a fourth well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well and the third well, and to be enclosed in the first well; and

a nonvolatile memory cell placed to two-dimensionally overlap with the second well, the third well and the fourth well,

the nonvolatile memory cell being equipped with;

a floating gate electrode placed to extend in a first direction so as to two-dimensionally overlap with the second well, the third well and the fourth well;

an element for programming and erasing data formed at a first position where the floating gate electrode two-dimensionally overlaps with the second well;

a field effect transistor for reading data formed at a second position where the floating gate electrode two-dimensionally overlaps with the third well; and

a capacitor element formed at a third position where the floating gate electrode two-dimensionally overlaps with the fourth well,

the element for programming and erasing data being equipped with;

a first electrode formed at the first position of the floating gate electrode;

a first insulating film formed between the first electrode and the semiconductor substrate;

a pair of second-conductivity type semiconductor regions formed in the second well at a position where the first electrode is sandwiched therebetween; and

the second well,

the field effect transistor for reading data being equipped with;

a second electrode formed at the second position of the floating gate electrode;

a second insulating film formed between the second electrode and the semiconductor substrate; and

a pair of first-conductivity-type semiconductor regions formed in the third well at a position where the second electrode is sandwiched therebetween,

the capacitor element being equipped with;

a third electrode formed at the third position of the floating gate electrode;

a third insulating film formed between the third electrode and the semiconductor substrate;

a pair of second-conductivity-type semiconductor regions formed in the fourth well at a position where the third electrode is sandwiched therebetween; and

the fourth well,

wherein the main circuit formation region has therein a low-breakdown-voltage field effect transistor driven at a first operating voltage and a high-breakdown-voltage field effect transistor driven at a second operating voltage higher than the first operating voltage,

wherein the data-read field effect transistor of the nonvolatile memory cell has a select field effect transistor electrically connected thereto so as to select the nonvolatile memory cell, and

wherein the thickness and gate length of a gate insulating film of the select field effect transistor are equal to the thickness and gate length of the low-break-voltage field effect transistor.

11. A semiconductor device according to claim 10, wherein a well for the formation of the select field effect transistor has been formed by the step employed for the formation of a well for the formation of the low-breakdown-voltage field effect transistor.

12. A semiconductor device, comprising:

a semiconductor substrate having a first main surface and, on the back side thereof, a second main surface;

a main circuit formation region placed over the first main surface of the semiconductor substrate; and

a nonvolatile memory region placed over the first main surface of the semiconductor substrate,

the nonvolatile memory region being equipped with;

a first well having a first conductivity type and formed over the main surface of the semiconductor substrate;

a second well having a second conductivity type, which type is opposite to the first conductivity type, and placed to be enclosed in the first well;

a third well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well, and to be enclosed in the first well;

a fourth well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well and the third well, and to be enclosed in the first well; and

a nonvolatile memory cell placed to two-dimensionally overlap with the second well, the third well and the fourth well,

the nonvolatile memory cell being equipped with;

a floating gate electrode placed to extend in a first direction so as to two-dimensionally overlap with the second well, the third well and the fourth well;

an element for programming and erasing data formed at a first position where the floating gate electrode two-dimensionally overlaps with the second well;

a field effect transistor for reading data formed at a second position where the floating gate electrode two-dimensionally overlaps with the third well; and

a capacitor element formed at a third position where the floating gate electrode two-dimensionally overlaps with the fourth well,

the element for programming and erasing data being equipped with;

a first electrode formed at the first position of the floating gate electrode;

a first insulating film formed between the first electrode and the semiconductor substrate;

a pair of semiconductor regions formed in the second well so as to sandwich therebetween the first electrode; and

the second well,

the field effect transistor for reading data being equipped with;

a second electrode formed at the second position of the floating gate electrode;

a second insulating film formed between the second electrode and the semiconductor substrate; and

a pair of first-conductivity-type semiconductor regions formed in the third well to sandwich therebetween the second electrode, and

the capacitor element being equipped with;

a third electrode formed at the third position of the floating gate electrode;

a third insulating film formed between the third electrode and the semiconductor substrate;

a pair of semiconductor regions formed in the fourth well to sandwich therebetween the third electrode; and

the fourth well,

wherein the semiconductor regions of the element for programming and erasing data constituting the pair have conductivity types opposite to each other, and

wherein the semiconductor regions of the capacitor element constituting the pair have each the second conductivity type.

13. A semiconductor device according to claim 12, wherein the floating gate electrode in an arrangement region of the element for programming and erasing data has both the first conductivity type semiconductor region and the second conductivity type semiconductor region.

14. A semiconductor device according to claim 13,

wherein the first conductivity type semiconductor region and the second conductivity type semiconductor region of the floating gate electrode in the arrangement region of the element for programming and erasing data are disposed so that the conductivity type of the floating gate electrode is separated into the first conductivity type and the second conductivity type along the second direction which is a direction crossing the first direction, and

wherein the conductivity type of the floating gate electrode is not separated into the first conductivity type and the second conductivity type along the first direction.

15. A semiconductor device according to claim 14, wherein the boundary between the first conductivity type semiconductor region and the second conductivity type semiconductor region, each of the floating gate electrode in the region where the element for programming and erasing data is placed, is disposed at the center of the second direction.

16. A semiconductor device according to claim 13,

wherein a silicide layer is formed over the upper surfaces of the pair of semiconductor regions of the element for programming and erasing data and the pair of semiconductor regions of the capacitor element, and

wherein not a silicide layer but an insulating film is formed over the upper surface of the floating gate electrode.

17. A semiconductor device according to claim 12, wherein the semiconductor regions of the element for programming and erasing data constituting the pair have one conductivity type so as to prevent the formation of the boundary between the first conductivity type and the second conductivity type in each region.

18. A semiconductor device, comprising:

a semiconductor substrate having a first main surface and, on the back side thereof, a second main surface;

a main circuit formation region placed over the first main surface of the semiconductor substrate; and

a nonvolatile memory region placed over the first main surface of the semiconductor substrate;

the nonvolatile memory region being equipped with;

a first well having a first conductivity type and formed over the main surface of the semiconductor substrate;

a second well having a second conductivity type, which type is opposite to the first conductivity type, and placed to be enclosed in the first well;

a third well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well, and to be enclosed in the first well;

a fourth well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well and the third well, and to be enclosed in the first well; and

a nonvolatile memory cell placed to two-dimensionally overlap with the second well, the third well and the fourth well,

the nonvolatile memory cell being equipped with;

a floating gate electrode placed to extend in a first direction so as to two-dimensionally overlap with the second well, the third well and the fourth well;

an element for programming and erasing data formed at a first position where the floating gate electrode two-dimensionally overlaps with the second well;

a field effect transistor for reading data formed at a second position where the floating gate electrode two-dimensionally overlaps with the third well; and

a capacitor element formed at a third position where the floating gate electrode two-dimensionally overlaps with the fourth well,

the element for programming and erasing data being equipped with;

a first electrode formed at the first position of the floating gate electrode, a first insulating film formed between the first electrode and the semiconductor substrate, a pair of semiconductor regions formed in the second well so as to sandwich therebetween the first electrode; and

the second well,

the field effect transistor for reading data being equipped with;

a second electrode formed at the second position of the floating gate electrode;

a second insulating film formed between the second electrode and the semiconductor substrate; and

a pair of first-conductivity-type semiconductor regions formed in the third well to sandwich therebetween the second electrode; and

the capacitor element being equipped with;

a third electrode formed at the third position of the floating gate electrode;

a third insulating film formed between the third electrode and the semiconductor substrate;

a pair of semiconductor regions formed in the fourth well to sandwich therebetween the third electrode; and

the fourth well,

wherein the semiconductor regions of the capacitor element constituting the pair have conductivity types opposite to each other, and

wherein the semiconductor regions of the element for programming and erasing data constituting the pair have each the second conductivity type.

19. A semiconductor device according to claim 18, wherein the floating gate electrode in the capacitor element arrangement region has both the first conductivity type semiconductor region and the second conductivity type semiconductor region.

20. A semiconductor device according to claim 19,

wherein the first conductivity type semiconductor region and the second conductivity type semiconductor region of the floating gate electrode in the capacitor element arrangement region are disposed so that the conductivity type of the floating gate electrode is separated into the first conductivity type and the second conductivity type along the second direction which is a direction crossing the first direction, and

wherein the conductivity type of the floating gate electrode is not separated into the first conductivity type and the second conductivity type along the first direction.

21. A semiconductor device according to claim 20, wherein the boundary between the first conductivity type semiconductor region and the second conductivity type semiconductor region, each of the floating gate electrode in the capacitor element arrangement region, is placed at the center, in the second direction, of the floating gate electrode.

22. A semiconductor device according to claim 19, wherein a silicide layer is formed over the upper surfaces of the pair of semiconductor regions of the element for programming and erasing data and the pair of semiconductor regions of the capacitor element, and

wherein not a silicide layer but an insulating film is formed over the upper surface of the floating gate electrode.

23. A semiconductor device according to claim 18, wherein the semiconductor regions of the capacitor element constituting the pair have one conductivity type so as to prevent the formation of a boundary between the first conductivity type and the second conductivity type.

24. A semiconductor device, comprising:

a semiconductor substrate having a first main surface and, on the back side thereof, a second main surface;

a main circuit formation region placed over the first main surface of the semiconductor substrate; and

a nonvolatile memory region placed over the first main surface of the semiconductor substrate,

the nonvolatile memory region being equipped with;

a first well having a first conductivity type and formed over the main surface of the semiconductor substrate;

a second well having a second conductivity type, which type is opposite to the first conductivity type, and placed to be enclosed in the first well;

a third well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well, and to be enclosed in the first well;

a fourth well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well and the third well, and to be enclosed in the first well; and

a nonvolatile memory cell placed to two-dimensionally overlap with the second well, the third well and the fourth well,

the nonvolatile memory cell being equipped with;

a floating gate electrode placed to extend in a first direction so as to two-dimensionally overlap with the second well, the third well and the fourth well;

an element for programming and erasing data formed at a first position where the floating gate electrode two-dimensionally overlaps with the second well;

a field effect transistor for reading data formed at a second position where the floating gate electrode two-dimensionally overlaps with the third well; and

a capacitor element formed at a third position where the floating gate electrode two-dimensionally overlaps with the fourth well,

the element for programming and erasing data being equipped with;

a first electrode formed at the first position of the floating gate electrode;

a first insulating film formed between the first electrode and the semiconductor substrate;

a pair of semiconductor regions formed in the second well at a position where the first electrode is sandwiched therebetween; and

the second well,

the field effect transistor for reading data being equipped with;

a second electrode formed at the second position of the floating gate electrode;

a second insulating film formed between the second electrode and the semiconductor substrate; and

a pair of first-conductivity-type semiconductor regions formed in the third well at a position wherein the second electrode is sandwiched therebetween, and

the capacitor element being equipped with;

a third electrode formed at the third position of the floating gate electrode;

a third insulating film formed between the third electrode and the semiconductor substrate;

a pair of semiconductor regions formed in the fourth well at a position where the third electrode is sandwiched therebetween; and

the fourth well,

wherein the semiconductor regions of the capacitor element constituting the pair have conductivity types opposite to each other, and

wherein the semiconductor regions of the element for programming and erasing data constituting the pair have conductivity types opposite to each other.

25. A semiconductor device according to claim 24, wherein the floating gate electrodes in the arrangement regions of the element for programming and erasing data and the capacitor element each has both the first conductivity type semiconductor region and the second conductivity type semiconductor region.

26. A semiconductor device according to claim 25,

wherein the first conductivity type semiconductor region and the second conductivity type semiconductor region of the floating gate electrode in each of the arrangement regions of the element for programming and erasing data and the capacitor element are disposed so that the conductivity type of the floating gate electrode is separated into the first conductivity type and the second conductivity type along the second direction, which is a direction crossing the first direction, and

wherein the conductivity type of the floating gate electrode is not separated into the first conductivity type and the second conductivity type along the first direction.

27. A semiconductor device according to claim 26, wherein the floating gate electrode in each of the arrangement regions of the element for programming and erasing data and the capacitor element has, at the center thereof in the second direction, the boundary between the first conductivity type semiconductor region and the second conductivity type semiconductor region.

28. A semiconductor device according to claim 25,

wherein a silicide layer is formed over the upper surfaces of the pair of semiconductor regions of the element for programming and erasing data and the pair of semiconductor regions of the capacitor element, and

wherein not a silicide layer but an insulating film is formed over the upper surface of the floating gate electrode.

29. A semiconductor device according to claim 24,

wherein the semiconductor regions of the element for programming and erasing data which constitute the pair have one conductivity type so as to prevent the formation of a boundary between the first conductivity type and the second conductivity type, and

wherein the semiconductor regions of the capacitor element constituting the pair have one conductivity type so as to prevent the formation of the boundary between the first conductivity type and the second conductivity type.