Boosting for non-volatile storage using channel isolation switching

• US 7,460,404 B1
• Filed: 05/07/2007
• Issued: 12/02/2008
• Est. Priority Date: 05/07/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Lee, Shih-Chung, Lutze, Jeffrey W., Hemink, Gerrit Jan, Dong, Yingda, Oowada, Ken
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US11/745,082
• Publication Number:
  US 20080279007A1
• Time in Patent Office: 575 Days
• Field of Search: 365/185.02
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits

Abstract

Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.

Claims

1. A method for operating non-volatile storage, comprising:

performing first boosting of at least one NAND string on a source side of a first word line before boosting the at least one NAND string on a drain side of a second word line, the second word line is on a drain side of the first word line, a plurality of word lines including the first and second word lines are associated with the at least one NAND string, and the at least one NAND string has a plurality of non-volatile storage elements;

during the first boosting, applying a voltage to the first word line for providing a first non-volatile storage element of the plurality of non-volatile storage elements which is associated with the first word line in a conducting state, and applying a voltage to the second word line for providing a second non-volatile storage element of the plurality of non-volatile storage elements which is associated with the second word line in a conducting state; and

performing second boosting of the at least one NAND string on the drain side of the second word line, after the first boosting, while applying a voltage to the first word line for providing the first non-volatile storage element in a non-conducting state, and while applying a program voltage to the second word line.

2. The method of claim 1, wherein:

during the second boosting, a voltage at a first level is applied to word lines of the plurality of word lines on the drain side of the second word line, the voltage applied to the first word line is at a second level which is less than the first level, and a voltage at a level greater than the second level is applied to at least one in between word line which is between the first word line and the second word line.

3. The method of claim 2, wherein:

during the second boosting, applying a voltage at a level which is between the first and second levels to a word line of the plurality of word lines which is between the at least one in between word line and the first word line.

4. The method of claim 2, wherein:

during the second boosting, applying a voltage at a level which is between the first and second levels to a word line of the plurality of word lines which is on the source side of the first word line, adjacent to the first word line.

5. The method of claim 1, further comprising:

during the first boosting, applying a voltage to at least one word line of the plurality of word lines which is between the first and second word lines for providing at least one non-volatile storage element of the plurality of non-volatile storage elements which is between the first and second word lines in a conducting state, so that every non-volatile storage element in the at least one NAND string between the first and second non-volatile storage elements is provided in a conducting state.

6. The method of claim 1, further comprising:

during the first boosting, applying a voltage to at least one word line of the plurality of word lines which is on the drain side of the second word line, adjacent to the second word line, for providing at least one non-volatile storage element of the plurality of non-volatile storage elements which is on the drain side of the second word line, adjacent to the second word line in a conducting state.

7. The method of claim 1, further comprising:

during the first boosting, applying a voltage to a set of word lines of the plurality of word lines which is on the drain side of the second word line for avoiding boosting of the at least one NAND string on the drain side of the second word line.

8. The method of claim 1, wherein:

the voltage applied to the second word line for providing the second non-volatile storage element in a conducting state is at a first level; and

the first boosting is performed by applying a voltage at a second level, greater than the first level, to a set of word lines of the plurality of word lines which is on the source side of the first word line.

9. The method of claim 1, wherein:

providing the first and second non-volatile storage elements in a conducting state allows charge transfer in the at least one NAND string between the source side of the first word line and the drain side of the second word line; and

providing the first storage element in a non-conducting state discourages charge transfer in the at least one NAND string between the source side of the first word line and the drain side of the second word line.

10. The method of claim 1, further comprising:

during the first boosting, applying a voltage to at least one word line of the plurality of word lines which is on the drain side of the second word line for providing at least a third non-volatile storage element of the plurality of non-volatile storage elements which is on the drain side of the second word line in a conducting state, and applying a voltage to a set of word lines of the plurality of word lines which is on a drain side of the at least a third non-volatile storage element, for avoiding boosting of the at least one NAND string on a drain side of the at least a third non-volatile storage element.

11. The method of claim 10, wherein:

the at least a third non-volatile storage element is adjacent to the second word line.

12. The method of claim 1, wherein:

the voltage applied to the first word line for providing the first non-volatile storage element in a conducting state is at a first level; and

the first boosting is performed by applying voltages at a second level, greater than the first level, to a set of non-volatile storage elements in the at least one NAND string which is on the source side of the first non-volatile storage element.

13. The method of claim 12, further comprising:

applying voltages at a third level, less than the first level, to a set of non-volatile storage elements of the plurality of non-volatile storage elements which is on a drain side of the second non-volatile storage element, while performing the first boosting.

14. The method of claim 13, further comprising:

applying voltages at the second level to the set of non-volatile storage elements in the at least one NAND string which is on the drain side of the second non-volatile storage element, while performing the second boosting.

15. The method of claim 1, wherein:

the second non-volatile storage element is programmed by the program voltage.

16. The method of claim 1, further comprising:

during the second boosting, applying a voltage to at least one of the word lines of the plurality of word lines which is between the first word line and the second word line for boosting the at least one NAND string between the first word line and the second word line.

17. The method of claim 1, further comprising, during the second boosting:

applying a voltage to an additional word line for providing an additional non-volatile storage element in a non-conducting state, the additional word line is on a drain side of the second word line, the second boosting is performed on a portion of the at least one NAND string which is between the second word line and the additional word line; and

performing third boosting of the at least one NAND string on a drain side of the additional word line.

18. A method for operating non-volatile storage, comprising:

performing first boosting of at least one NAND string on a side of a first non-volatile storage element in the at least one NAND string which is before the first non-volatile storage element in a programming sequence;

during the first boosting, providing the first non-volatile storage element and a second non-volatile storage element in the at least one NAND string which is on a side of the first non-volatile storage element which is after the first non-volatile storage element in the programming sequence in a conducting state; and

performing second boosting of the at least one NAND string, after the first boosting, on a side of the second non-volatile storage element which is after the second non-volatile storage element in the programming sequence while providing the first storage element in a non-conducting state.

19. The method of claim 18, further comprising:

during the second boosting, applying a program voltage to a word line associated with the second non-volatile storage element.

20. The method of claim 18, wherein:

the programming sequence starts at a source side of the at least one NAND string and ends at a drain side of the at least one NAND string.

21. The method of claim 18, wherein:

the side of the first non-volatile storage element which is before the first non-volatile storage element in the programming sequence includes non-volatile storage elements in the at least one NAND string which are fully programmed; and

the side of the second non-volatile storage element which is after the second non-volatile storage element in the programming sequence includes non-volatile storage elements in the at least one NAND string which are unprogrammed and/or partially programmed.

22. The method of claim 18, wherein:

the side of the first non-volatile storage element which is before the first non-volatile storage element in the programming sequence has undergone programming operations, since a last erase operation, needed to fully program a non-volatile storage element; and

the side of the second non-volatile storage element which is after the second non-volatile storage element in the programming sequence has not undergone programming operations, since the last erase operation, needed to fully program a non-volatile storage element.

23. The method of claim 18, further comprising:

during the first boosting, providing at least one non-volatile storage element which is between the first and second non-volatile storage elements in a conducting state, so that every non-volatile storage element in the at least one NAND string between the first and second non-volatile storage element is provided in a conducting state.

24. The method of claim 18, further comprising:

during the first boosting, providing at least one non-volatile storage element which is on the side of the second non-volatile storage element which is after the second non-volatile storage element in the programming sequence in a conducting state, and adjacent to the second non-volatile storage element.

25. The method of claim 18, further comprising:

during the first boosting, avoiding boosting of a set of non-volatile storage elements which is on the side of the second non-volatile storage element which is after the second non-volatile storage element in the programming sequence.

26. A method for operating non-volatile storage, comprising:

(a) in a first time period;

(i) applying voltages to a first set of word lines on a source side of a particular word line in a set of word lines for boosting a first channel region of at least one NAND string;

(ii) applying voltages to a second set of word lines which includes the particular word line, the second set of word lines is on a drain side of the first set of word lines, to provide non-volatile storage elements in the at least one NAND string which are associated with the second set of word lines in a conducting state; and

(iii) applying voltages to a third set of word lines on a drain side of the second set of word lines, to avoiding boosting of a second channel region of the at least one NAND string; and

(b) in a second time period which follows the first time period;

(i) applying voltages to the third set of word lines for boosting the second channel region of the at least one NAND string;

(ii) applying a program voltage to a word line in the second set of word lines; and

(iii) applying a voltage to the particular word line to isolate the first channel region from the second channel region.

27. The method of claim 26, wherein:

the voltages in steps (a)(i) and (b)(i) are the same.

28. The method of claim 26, wherein:

the voltages in step (a)(ii) are lower than the voltages in step (a)(i) but higher than the voltages in step (a)(iii).

29. The method of claim 26, wherein:

the program voltage is greater than the voltages in step (a)(i).

30. The method of claim 26, further comprising:

during the second boosting, applying a voltage to at least one of the word lines of the plurality of word lines which is between the particular word line and the word line to which the program voltage is applied, for boosting the at least one NAND string between the particular word line and the word line to which the program voltage is applied.

31. The method of claim 26, further comprising:

during the second time period, applying voltages to a fourth set of word lines on a drain side of the third set of word lines for boosting a third channel region of the at least one NAND string on a drain side of the second channel region, and applying a voltage to a word line between the second and third channel regions for isolating the second and third channel regions from each other.

32. The method of claim 26, further comprising:

in step (a)(ii) the voltages applied to the second set of word lines are set based on programmed states of the non-volatile storage elements in the at least one NAND string which are associated with the second set of word lines.

33. The method of claim 26, further comprising:

in step (a)(ii) the voltages applied to the second set of word lines include a higher voltage which is applied to a non-volatile storage element with a higher programmed state, and a lower voltage which is applied to a non-volatile storage element with a lower programmed state.