Nonvolatile semiconductor memory device and programming or erasing method therefor

• US 7,460,410 B2
• Filed: 08/11/2006
• Issued: 12/02/2008
• Est. Priority Date: 09/01/2005
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Misumi, Kenji, Toki, Masahiro, Kotani, Hideto, Nagai, Hiroyasu
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US11/502,430
• Publication Number:
  US 20070047318A1
• Time in Patent Office: 844 Days
• Field of Search: 365/185.09
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

In a nonvolatile memory cell having a trap layer, programming or erasing is made in a sequence of first charge injection with a given wait time being secured and second charge injection executed after the first charge injection. Surrounding charge that deteriorates the data retention characteristic is reduced by use of initial variation occurring immediately after programming (charge loss phenomenon due to binding of injected charge with the surrounding charge in an extremely short time), and then the charge loss due to the initial variation is compensated, to thereby improve the data retention characteristic.

Claims

1. A programming or erasing method for a nonvolatile semiconductor memory device having a trap layer, the method comprising, during programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

wherein in the first charge injection step, a given wait time is secured after charge injection is executed until reaching a given threshold voltage,

in the second charge injection step, charge injection is executed until reaching a given threshold voltage, and

the wait time is longer than the time required for a normal verify operation or read operation.

2. A programming or erasing method for a nonvolatile semiconductor memory device having a trap layer, the method comprising, during programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

wherein in the first charge injection step, a given wait time is secured after charge injection is executed until reaching a given threshold voltage,

in the second charge injection step, charge injection is executed until reaching a given threshold voltage, and

the wait time is the time required for binding of first charge trapped in the first charge injection step with surrounding charge opposite to the first charge already trapped before the first charge injection step.

3. A programming or erasing method for a nonvolatile semiconductor memory device having a trap layer, the method comprising, during programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

wherein in the first charge injection step, a given wait time is secured after charge injection is executed until reaching a given threshold voltage,

in the second charge injection step, charge injection is executed until reaching a given threshold voltage, and

as the wait time, the time of operation other than the second charge injection step for the memory cell for which the first charge injection has been executed is utilized.

4. A programming or erasing method for a nonvolatile semiconductor memory device having a trap layer, the method comprising, during programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

wherein in the first charge injection step, a given wait time is secured after charge injection is executed until reaching a given threshold voltage,

in the second charge injection step, charge injection is executed until reaching a given threshold voltage, and

the wait time can be set with a timer circuit so that a fixed time or longer is maintained for a memory cell targeted for programming or erasing.

5. A programming or erasing method for a nonvolatile semiconductor memory device having a trap layer, the method comprising, during programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

wherein in the first charge injection step, a given wait time is secured after charge injection is executed until reaching a given threshold voltage,

in the second charge injection step, charge injection is executed until reaching a given threshold voltage, and

two different verify levels are provided, and assuming that one having a lower threshold voltage is called the first verify level and the other having a higher threshold voltage is called the second verify level, the first charge injection step is executed until reaching the first verify level, and the second charge injection step is executed until reaching the second verify level.

6. A programming or erasing method for a nonvolatile semiconductor memory device having a trap layer, the method comprising, during programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

wherein in the first charge injection step, a given wait time is secured after charge injection is executed until reaching a given threshold voltage,

in the second charge injection step, charge injection is executed until reaching a given threshold voltage, and

two different verify levels are provided, and assuming that one having a lower threshold voltage is called the first verify level and the other having a higher threshold voltage is called the second verify level, the first charge injection step is executed until reaching the second verify level, and the second charge injection step is executed until reaching the first verify level.

7. A nonvolatile semiconductor memory device having a trap layer, the device comprising:

a programming or erasing sequence control circuit for controlling, so that first charge injection and second charge injection are executed during programming or erasing, a given wait time after charge injection is executed until reaching a given memory cell threshold voltage in the first charge injection and also controlling the second charge injection after the lapse of the given wait time;

a programming data recognition circuit for recognizing data programmed in the first charge injection; and

an input data switch circuit capable of switching between the data recognized by the programming data recognition circuit and programming data input externally.

8. A nonvolatile semiconductor memory device having a trap layer, the device comprising:

a programming or erasing sequence control circuit for controlling, so that first charge injection and second charge injection are executed during programming or erasing, a given wait time after charge injection is executed until reaching a given memory cell threshold voltage in the first charge injection and also controlling the second charge injection after the lapse of the given wait time;

a first programming data hold circuit capable of holding data;

a second programming data hold circuit capable of holding data and copying data bidirectionally with the first programming data hold circuit, the second programming data hold circuit having a capacity greater than the first programming data hold circuit; and

a data copying control circuit for controlling data transfer between the first programming data hold circuit and the second programming data hold circuit.