Flash memory device and erasing method thereof

• US 7,460,412 B2
• Filed: 12/29/2006
• Issued: 12/02/2008
• Est. Priority Date: 07/31/2006
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Jong-In, Lee, Doo-Sub
• Primary Examiner(s): Pham; Ly D
• Application Number:
  US11/617,939
• Publication Number:
  US 20080049493A1
• Time in Patent Office: 704 Days
• Field of Search: 365/185.2, 365/185.22, 365/236, 365/239, 365/185.3
• US Class Current: 365/185.3
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing

Abstract

A method of post-programming a flash memory device includes the steps of: post-programming memory cells of a selected word line in a predetermined unit; determining, after incrementing an address for selecting the next word line, whether the incremented address matches one of reference addresses; and varying the post-programming unit of the selected memory cells whenever the incremented address matches one of reference addresses.

Claims

1. A method of post-programming a flash memory device, comprising the steps of:

(a) post-programming memory cells of a selected word line from a plurality of word lines in a predetermined unit;

(b) determining, after incrementing an address for selecting the next word line, whether the incremented address matches one of a plurality of reference addresses; and

(c) varying the post-programming unit of the memory cells whenever the incremented address matches one of the plurality of reference addresses.

2. The method as set forth in claim 1, wherein the post-programming unit of the selected memory cells is incremented whenever the incremented address matches one of the plurality of reference addresses.

3. The method as set forth in claim 1, wherein the post-programming unit of the selected memory cells is changed by controlling a number of write drivers activated at a same time.

4. The method as set forth in claim 1, wherein the steps of (a) through (c) are repeated until all word lines are selected.

5. The method as set forth in claim 1, wherein the plurality of reference addresses are stored in a register of the flash memory device.

6. The method as set forth in claim 5, wherein the plurality of reference addresses are externally provided to the register before a normal operation.

7. The method as set forth in claim 5, wherein the plurality of reference addresses are provided to the register from an array of the flash memory device before a normal operation.

8. A method of post-programming a flash memory device, comprising the steps of:

(a) selecting a word line from a plurality of word lines in response to an address;

(b) post-programming memory cells of the selected word line in a predetermined post-programming unit;

(c) determining, after incrementing the address, whether the incremented address matches one of a plurality of reference addresses;

(d) varying the post-programming unit of the selected memory cells whenever the incremented address matches one of the plurality of reference addresses; and

(e) repeating the steps (a) through (d) until all word lines are selected.

9. The method as set forth in claim 8, wherein the post-programming unit of the selected memory cells is incremented whenever the incremented address matches one of the plurality of reference addresses.

10. The method as set forth in claim 8, wherein the post-programming unit of the selected memory cells is changed by controlling a number of write drivers activated at a same time.

11. A flash memory device having a memory cell array with memory cells arranged in rows and columns, comprising:

a row decoder selecting the rows in response to a row address;

a column decoder selecting the columns in response to a column address;

write drivers divided into a plurality of groups for driving the selected columns with a bit line voltage;

a column address generator counting a number of post-programming operations and generating the column address and a count-up pulse signal;

a row address generator configured to store a plurality of reference addresses, generating the row address in response to the count-up pulse signal; and

a selection circuit generating selection signals to activate each of the write driver groups in response to a counted value of the count-up pulse signal,

wherein the row address generator outputs flag information indicating a change of column selection unit whenever the row address matches one of the plurality of reference addresses, and

wherein the selection circuit controls activation of the selection signals in accordance with the flag information so as to increase a number of the memory cells to be post-programmed in the selected columns.

12. The flash memory device as set forth in claim 11, wherein the column address generator outputs the count-up pulse signal when memory cells of the selected row are all post-programmed.

13. The flash memory device as set forth in claim 11, wherein the write drivers of each of the plurality of groups, when a corresponding selection signal is activated, are set in a program value to drive corresponding bit lines with a bit line voltage.

14. The flash memory device as set forth in claim 11, wherein the row address generator comprises a register for storing the plurality of reference addresses.

15. The flash memory device as set forth in claim 14, wherein the plurality of reference addresses are externally provided to the register before a normal operation.

16. The flash memory device as set forth in claim 14, wherein the plurality of reference addresses are provided to the register from the memory cell array before a normal operation or at a power-up time.

17. The flash memory device as set forth in claim 11, wherein the flag information informs that the columns are selected in the column selection unit selected from ×

4, ×

8, and ×

16.

18. The flash memory device as set forth in claim 17, wherein when the flag information informs that the columns are selected in the unit of ×

4, the selection circuit activates the selection signals in sequence in response to the counted value.

19. The flash memory device as set forth in claim 17, wherein when the flag information informs that the columns are selected in the unit of ×

8, the selection circuit activates pairs of the selection signals in sequence in response to the counted value.

20. The flash memory device as set forth in claim 17, wherein when the flag information informs that the columns are selected in the unit, of ×

16, the selection circuit activates the selection signals at the same time in response to the counted value.

21. The flash memory device as set forth in claim 11, wherein the column address generator comprises:

a 2-bit counter conducting a counting operation in accordance with a transition of a program execution signal instructing the post-programming operation and outputting a pulse signal whenever a carry is generated; and

an N-bit counter generating the column address from a counting operation in accordance with the pulse signal and generating the count-up pulse signal when the columns are all selected.

22. The flash memory device as set forth in claim 21, wherein the 2-bit counter is configured to vary a point of generating the carry in accordance with the flag information.

23. The flash memory device as set forth in claim 11, wherein the post-programming operation includes a verifying operation.

24. The flash memory device as set forth in claim 11, wherein the post-programming operation is carried out without including a verifying operation.