Modulation noise estimation mechanism

• US 7,460,499 B2
• Filed: 01/16/2004
• Issued: 12/02/2008
• Est. Priority Date: 01/17/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Staszewski, Bogdan, Eliezer, Oren, Friedman, Ofer
• Primary Examiner(s): SINGH, RAMNANDAN P
• Application Number:
  US10/758,913
• Publication Number:
  US 20040146098A1
• Time in Patent Office: 1,782 Days
• Field of Search: 370/286
• US Class Current: 370/286
• CPC Class Codes: H03C 3/0941 applying frequency modulation at more than one point in the loop
• CPC Class Codes: H03C 3/095 applying frequency modulation to the loop in front of the voltage controlled oscillator
• CPC Class Codes: H03C 3/0966 modulating the reference clock
• CPC Class Codes: H03C 3/0991 including calibration means or calibration methods
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop

Abstract

An on-chip reduced complexity modulation noise estimation mechanism for performing nonlinear signal processing to analyze modulation noise to determine whether a semiconductor device under test complies with the performance criteria set by specifications or a standard corresponding thereto. When used in a two-point transmitter modulation architecture, the mechanism relies on the fact that the noise statistics at the output of the transmitter can be determined by observing the phase error output of the phase detector within the phase locked loop. In the digital embodiment of the mechanism, the phase error signal is compared to a configurable threshold value to generate an exception event. If the number of exception events exceeds a configurable max_fail value after comparisons of a configurable number of phase error samples, the test fails. A pass/fail signal is output reflecting the result of the test. The test comprises a configurable number of test samples to permit flexibility in the tradeoff between the time required to complete the test versus the statistical reliability of the test result, i.e. the probability of it correctly determining whether the tested device complies with target specifications.

Claims

1. A method of testing an oscillator within a phase locked loop, said method comprising the steps of:

averaging phase error samples produced by said phase locked loop, wherein said phase error samples correspond to the phase noise of said oscillator;

subtracting said average from a current phase error sample to yield a normalized phase error;

generating an exception event if said normalized phase error exceeds a threshold, thereby indicating that the level of oscillator phase noise is not acceptable; and

repeating said steps of averaging, subtracting and generating over a period of time and outputting a test failure indication if the number of exception events exceeds a maximum criterion and a test pass indication otherwise.

2. The method according to claim 1, wherein said step of averaging comprises the step of calculating a moving average over a plurality of phase error samples.

3. The method according to claim 1, wherein said threshold is configurable.

4. The method according to claim 1, wherein said maximum failure criterion is configurable.

5. The method according to claim 1, wherein said period of time is configurable and corresponds to the number of symbols to be considered in estimating said phase noise.

6. The method according to claim 1, further comprising the step of decimating said phase error samples before said step of averaging.

7. The method according to claim 1, implemented in testing software residing in an integrated on-chip processor thereby eliminating the need for external software and hardware to implement said method.

8. The method according to claim 1, wherein said phase error samples comprise filtered phase error samples.

9. The method according to claim 1, wherein said phase locked loop is used as the local oscillator for a transceiver compliant with a Bluetooth standard.

10. The method according to claim 1, wherein said phase locked loop is used in a transceiver within a wireless communications network.

11. The method according to claim 1, wherein the phase locked loop comprises a digital phase locked loop.

12. The method according to claim 1, implemented in an Application Specific Integrated Circuit (ASIC).

13. The method according to claim 1, implemented in a Field Programmable Gate Array (FPGA).

14. An apparatus for testing an oscillator in a phase locked loop having a phase locked loop, comprising:

means for averaging phase error samples produced by said phase locked loop;

means for subtracting said average from a current phase error sample to yield a normalized phase error, wherein said normalized phase error corresponds to the phase modulation noise of said oscillator;

means for generating an exception event if said normalized phase error exceeds a threshold; and

means for repeating said functions of averaging, subtracting and generating over a period of time and outputting a test failure indication if the number of exception events exceeds a maximum criterion and a test pass indication otherwise.

15. The apparatus according to claim 14, wherein said means for averaging comprises means for calculating a moving average over a plurality of phase error samples.

16. The apparatus according to claim 14, wherein said threshold is configurable.

17. The apparatus according to claim 14, wherein said maximum failure criterion is configurable.

18. The apparatus according to claim 14, wherein said period of time is configurable.

19. The apparatus according to claim 14, further comprising means for decimating said phase error samples before said average is calculated.

20. The apparatus according to claim 14, implemented in testing software adapted to execute on an on-chip software based processor.

21. The apparatus according to claim 20, wherein said testing software is stored in rewritable memory wherein said testing software is replaced by normal operation software once testing is complete.

22. The apparatus according to claim 14, implemented in an Application Specific Integrated Circuit (ASIC).

23. The apparatus according to claim 14, implemented in a Field Programmable Gate Array (FPGA).

24. An apparatus for testing an oscillator in a phase locked loop, comprising:

first means for measuring a phase error signal within said phase locked loop, wherein said phase error signal corresponds to the phase noise of said oscillator;

second means for comparing a plurality of phase error signal samples over a period of time to a threshold and generating an exception event each time a phase error signal sample exceeds said threshold; and

generating a test failure indication if the number of exception events exceeds a defined limit and generating a test pass indication otherwise.

25. The apparatus according to claim 24, wherein said phase error signal comprises a digital sample.

26. The apparatus according to claim 24, wherein said phase error signal comprises an analog sample.

27. The apparatus according to claim 24, wherein said threshold is configurable.

28. The apparatus according to claim 24, wherein said criteria is configurable.

29. The apparatus according to claim 24, wherein said period of time is configurable.

30. The apparatus according to claim 24, wherein said threshold is configured to correspond to a particular noise threshold on a modulation noise probability density function.

31. The apparatus according to claim 24, wherein lowering said threshold causes the number of exception events to increase for the same criteria and period of time and increasing said threshold causes the number of exception events to decrease for the same criteria and period of time.

32. The method according to claim 24, implemented in testing software adapted to execute on an embedded microprocessor or digital signal processor.

33. The apparatus according to claim 32, wherein said testing software is stored in rewritable memory wherein said testing software is replaced by normal operation software once testing is complete.

34. The apparatus according to claim 24, implemented in an Application Specific Integrated Circuit (ASIC).

35. The apparatus according to claim 24, implemented in a Field Programmable Gate Array (FPGA).

36. A method of testing an oscillator in a phase locked loop, said method comprising the steps of:

generating a normalized phase error signal from a plurality of phase error samples generated by said phase locked loop; and

counting the number of times said normalized phase error signal crosses a threshold within a predefined period of time, wherein the count represents an estimate of the phase modulation noise of said oscillator; and

failing said oscillator if said count exceeds a predefined maximum, and passing said oscillator otherwise.

37. The method according to claim 36, wherein said maximum corresponds to a modulation quality requirement of a particular standard.