Networking methods and systems
First Claim
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1. A network system, comprising:
- a direct conversion radio transceiver coupled to a digitizer, integrated within a first integrated device;
a medium access controller coupled between a baseband processor and digital control circuitry, integrated within a second integrated device; and
a digital interface that couples said first integrated device to said second integrated device;
wherein said digitizer comprises;
a in-phase receive path analog-to-digital converter;
a quadrature-phase receive path analog-to-digital converter;
a in-phase transmit path digital-to-analog converter; and
a quadrature-phase transmit path digital-to-analog converter;
wherein said digital interface comprises transceiver-side digital interface circuitry, including;
a plurality of latches coupled to said digital-to-analog converters and to said analog-to-digital converters;
a bi-directional bus driver coupled between said plurality of latches and a bi-directional bus; and
address control and timing circuitry coupled to said latches; and
wherein said digital interface further comprises controller-side digital interface circuitry, including;
a second bi-directional bus driver coupled to said bi-directional bus;
a second plurality of latches coupled between said second bi-directional bus driver and said baseband processor; and
second address control and timing circuitry coupled to said second plurality of latches.
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Abstract
A network system includes integrated radio transceivers and digitizers, integrated baseband processors and device controllers, digital interfaces there between, and architectures and partitions for same. Licensing methodologies are provided for implementing the features described herein, and for other products and services.
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Citations
36 Claims
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1. A network system, comprising:
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a direct conversion radio transceiver coupled to a digitizer, integrated within a first integrated device; a medium access controller coupled between a baseband processor and digital control circuitry, integrated within a second integrated device; and a digital interface that couples said first integrated device to said second integrated device; wherein said digitizer comprises; a in-phase receive path analog-to-digital converter; a quadrature-phase receive path analog-to-digital converter; a in-phase transmit path digital-to-analog converter; and a quadrature-phase transmit path digital-to-analog converter; wherein said digital interface comprises transceiver-side digital interface circuitry, including; a plurality of latches coupled to said digital-to-analog converters and to said analog-to-digital converters; a bi-directional bus driver coupled between said plurality of latches and a bi-directional bus; and address control and timing circuitry coupled to said latches; and wherein said digital interface further comprises controller-side digital interface circuitry, including; a second bi-directional bus driver coupled to said bi-directional bus; a second plurality of latches coupled between said second bi-directional bus driver and said baseband processor; and second address control and timing circuitry coupled to said second plurality of latches. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 32, 33, 34, 35)
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17. A network system, comprising:
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a direct conversion radio transceiver; a baseband processor; a digitizer coupled between said direct conversion radio transceiver and said baseband processor; and a digital interface coupled to said baseband processor, said digital interface configured to couple to a medium access controller; wherein said direct conversion radio transceiver, said baseband processor, and said digitizer are integrated in an integrated device; wherein said digitizer comprises; a in-phase receive path analog-to-digital converter; a quadrature-phase receive path analog-to-digital converter; a in-phase transmit path digital-to-analog converter; and a quadrature-phase transmit path digital-to-analog converter; wherein said digital interface comprises transceiver-side digital interface circuitry, including; a plurality of latches coupled to said baseband processor; a bi-directional bus driver coupled between said plurality of latches and a bi-directional bus; and address control and timing circuitry coupled to said latches; and wherein said digital interface further comprises controller-side digital interface circuitry, including; a second bi-directional bus driver coupled to said bi-directional bus; a second plurality of latches coupled between said second bi-directional bus driver and said medium access controller; and second address control and timing circuitry coupled to said second plurality of latches. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 36)
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Specification
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Current AssigneeParkerVision, Inc.
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Original AssigneeParkerVision, Inc.
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InventorsSorrells, David F., Parker, Jeffrey L.
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Primary Examiner(s)Fan; Chieh M.
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Assistant Examiner(s)Aghdam; Freshteh N.
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Application NumberUS10/197,255Publication NumberTime in Patent Office2,329 DaysField of Search375/219, 375/316, 375/324US Class Current375/219CPC Class CodesH04B 1/30 for homodyne or synchrodyne...H04L 27/00 Modulated-carrier systems
