Segmented on-chip memory and requester arbitration
First Claim
1. A WLAN (Wireless Local Area Network) communication device adapted to be 802.11 compliant, the WLAN communication device comprising:
- an on-chip memory adapted to buffer data frames received and/or to be transmitted by the WLAN communication device, said on-chip memory having separate, individually addressable memory segments, wherein said separate, individually addressable memory segments are physical memory segments;
at least one interface interfacing to at least one external device; and
an arbitration unit connected to said on-chip memory and said at least one interface to control access of multiple requesters to the separate, individually addressable memory segments, at least one of said multiple requesters being said at least one external device.
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Accused Products
Abstract
A memory access technique is provided that may be used in WLAN (Wireless Local Area Network) communication devices. An on-chip memory has multiple memory circuits forming individually addressable memory segments. An arbitration unit arbitrates between multiple requesters, each requesting access to the on-chip memory. The requesters are on-chip circuits and/or external devices. The arbitration unit determines a memory circuit to be accessed for each request that is received from a requester. The determination may be based on a software configurable arbitration scheme. The memory segments may form a bank of single-port SRAM (Static Random Access Memory) devices.
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Citations
73 Claims
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1. A WLAN (Wireless Local Area Network) communication device adapted to be 802.11 compliant, the WLAN communication device comprising:
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an on-chip memory adapted to buffer data frames received and/or to be transmitted by the WLAN communication device, said on-chip memory having separate, individually addressable memory segments, wherein said separate, individually addressable memory segments are physical memory segments; at least one interface interfacing to at least one external device; and an arbitration unit connected to said on-chip memory and said at least one interface to control access of multiple requesters to the separate, individually addressable memory segments, at least one of said multiple requesters being said at least one external device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. An integrated circuit chip comprising:
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an on-chip memory having multiple memory circuits forming individually addressable memory segments; and an arbitration circuit adapted to arbitrate between multiple requesters each requesting access to said on-chip memory, said requesters being on-chip circuits and/or external devices coupled to said integrated circuit chip, said arbitration circuit adapted to determine, for each request received from a requester, a memory circuit to be accessed, wherein said determination is based on a software configurable arbitration scheme. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70)
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71. A memory device comprising:
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an on-chip bank of single-port SRAM (Static Random Access Memory) devices, wherein said on-chip bank of single-port SRAM devices has a data port and an address port, said address port coupleable to an arbiter for having access of multiple requesters to said on-chip bank controlled by selecting at least one of said single-port SRAM devices and physically address memory cells in the selected single-port SRAM device.
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72. A method of controlling access to an on-chip memory, comprising:
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receiving requests from multiple requesters to read data from and/or write data to said on-chip memory; determining which one of the received requests is to be served next; for the determined request, determining which one of multiple separate, individually addressable memory segments of said on-chip memory is to be used, wherein said separate, individually addressable memory segments are physical memory segments; and addressing a memory cell in the determined memory segment to read or write data to or from said memory cell in compliance with the determined request.
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73. A computer readable storage medium storing instructions that, when executed by a processor, cause said processor to configure an arbiter to arbitrate between multiple requesters each requesting access to an on-chip memory having multiple separate, individually addressable memory segments by determining, for each request received from a requester, a memory segment to be accessed and addressing a memory cell in the determined memory segment to read or write data to or from said memory cell in compliance with the determined request.
Specification