Method and system for dynamically adjusting data transfer rates in PCI-express devices

• US 7,461,195 B1
• Filed: 03/17/2006
• Issued: 12/02/2008
• Est. Priority Date: 03/17/2006
• Status: Expired due to Fees

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: QLogic Corporation (Marvell Technology Group Limited)
• Inventors: Woodral, David E
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US11/378,838
• Time in Patent Office: 991 Days
• Field of Search: 710/107, 710/313, 710/104, 710/316
• US Class Current: 710/313
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

Method and system for configuring a PCI-Express device is provided. The method includes determining if a number of lanes supported by the PCI-Express device is equal to or greater than a number X, after a receiver is detected by the PCI-Express device; and setting a transfer rate depending on the number X. The PCI-Express Device includes PCI-Express core logic that receives information from a Physical Coding Sub-layer indicating if a number of lanes supported by the PCI-Express device is equal to or greater than a number X, after a receiver is detected; and a transfer rate is set depending on the number X. The value of X depends on the PCI-Express device'"'"'s throughput capability and a data transfer rate.

Claims

1. A method for configuring an adapter operationally coupled to a host system, comprising:

determining if a number of lanes supported by the adapter is greater than a number X, after a receiver is detected by the adapter;

wherein X depends on a throughput capability of the adapter and a data transfer rate; and

setting a first lane operating speed if the number of lanes is less than the number X and setting a second lane operating speed if the number of lanes is greater than the number X.

2. The method of claim 1 wherein the number X is determined by dividing the throughput capability by the data transfer rate.

3. The method of claim 1, wherein a state machine in a physical layer of a core logic performs lane configuration after receiving information regarding the number of lanes supported by the adapter.

4. The method of claim 3, wherein the state machine, based on the number of lanes supported by the adapter, sets certain bit values of a first training packet and a second training packet to broadcast link operating speeds.

5. The method of claim 4, wherein if X is equal to or less than 4, then an operating speed of 5 Ghz is set and during a speed negotiation step, the adapter and another device enter an idle state for a duration during which the first training packet and the second training packet are re-transmitted and both the adapter and the other device initiate a change in operating speed based on information embedded in the re-transmitted first training packet and the second training packet.

6. The method of claim 1 wherein if X is greater than 4, then an operating speed of 2.5 GHz is set.

7. The method of claim 1, wherein the adapter is a host bus adapter.

8. An adapter operationally coupled to a host system, comprising:

a core logic that receives information from a Physical Coding Sub-layer indicating if a number of lanes supported by the adapter is greater than a number X, after a receiver is detected;

wherein X depends on a throughput capability of the adapter and a data transfer rate; and

a first lane operating speed is set if the number of lanes is less than the number X and a second lane operating speed is set if the number of lanes is greater than the number X.

9. The adapter of claim 8, wherein the number X is determined by dividing the throughput capability by the data transfer rate.

10. The adapter of claim 8, wherein a state machine in a physical layer of the core logic performs lane configuration after receiving information regarding the number of lanes supported by the adapter.

11. The adapter of claim 10, wherein the state machine, based on the number of lanes supported by the adapter, sets certain bit values of a first training packet and a second training packet to broadcast link operating speeds.

12. The adapter of claim 11, wherein if X is equal to or less than 4, then an operating speed of 5 Ghz is set and during a speed negotiation step, the adapter and another device enter an idle state for a duration during which the first training packet and the second training packet are re-transmitted and both the adapter and the other device initiate a change in operating speed based on information embedded in the re-transmitted first training packet and the second training packet.

13. The adapter of claim 8, wherein if X is greater than 4, then an operating speed of 2.5 GHz is set.

14. The adapter of claim 8, wherein the adapter is a host bus adapter.

15. The adapter of claim 14, wherein the host bus adapter is operationally coupled to a computing system for transferring data to and from a storage area network.

16. The adapter of claim 8, wherein the PCI-Express device is operationally coupled to another PCI-Express device for transferring data.