System and method for configuration and management of flash memory

• US 7,461,198 B2
• Filed: 07/21/2006
• Issued: 12/02/2008
• Est. Priority Date: 07/29/2005
• Status: Active Grant

• Current Assignee: Genesys Logic Incorporated
• Original Assignee: Genesys Logic Incorporated
• Inventors: Kuo, Tei-Wei, Chang, Yuan-Hao, Hsieh, Jen-Wei, Tsai, Yi-Lin, Hsieh, Hsiang-Chi
• Primary Examiner(s): Ellis; Kevin L
• Assistant Examiner(s): Bertram; Ryan
• Application Number:
  US11/490,049
• Publication Number:
  US 20070038802A1
• Time in Patent Office: 865 Days
• Field of Search: 711/103
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block. By forming correspondence among the physical erase unit, segment, frame, page, virtual erase unit, area, memory logical block and cluster to control the data access to the flash memory, the present invention achieves the reconfiguration and management of memory consumption and access efficiency for the flash memory.

Claims

1. A method for configuration and management of flash memory, comprising the following steps:

(a) defining a relationship among a flash memory, a virtual memory region, and a memory logical block region according to a logical block address of the write request to said flash memory;

(b) defining a plurality of data access basic control units of said flash memory, including physical erase unit, segment, frame, and page, by configuring the structure of said flash memory of step (a) into said physical erase unit, said segment, said frame and said page;

(c) defining a plurality of data access basic control units of the virtual memory region, including virtual erase unit and area, by configuring the structure of said virtual memory region of step (a) into said area and said virtual erase unit;

(d) defining a plurality of data access basic control units of the memory logical block region, including cluster and logical block, by configuring the structure of said memory block region of step (a) into said cluster and said logical block;

(e) constructing an erase unit table, a cluster table and a free segment table according to a relationship among the physical erase unit, segment, virtual erase unit, area, logical block and cluster, by using said physical erase unit, said segment of step (b), said area, said virtual erase unit of step (c), said cluster, said logical block of step (d) to construct said erase unit table, said cluster table and said free segment table; and

(f) processing data access according to a relationship in said erase unit table, said cluster table, and said free segment table, by using said erase unit table, said cluster table and said free segment table of step (e) to map a read or write request to said logical block of said memory logical block region to a read or write operation to said frame of said flash memory.

2. The method as claimed in claim 1, wherein the relationship between said area and said cluster of step (e) is an area number equal to the modulo of a cluster number divided by the number of said areas.

3. The method as claimed in claim 1, wherein a divider is connected between said logical block address of said logical block and said cluster table of step (e), and a modulo unit is connected between said erase unit table and said divider.

4. The method as claimed in claim 1, wherein a divider and a modulo unit are connected in series between said logical block address of said logical block and said erase unit table, said free segment table of step (e).

5. The method as claimed in claim 1, wherein step (f) is to construct a cluster register in said flash memory, further comprising the following steps:

(f1) issuing read or write request to a logical block;

(f2) determining whether said request is a read request or a write request, if it is a read request, proceeding to step (f3);

otherwise, proceeding to step (f9);

(f3) determining whether the cluster said logical block belonging to is currently in said cluster register;

if so, proceeding to step (f7);

otherwise, proceeding to step (f4);

(f4) determining whether the data of said cluster currently in said cluster register have been modified;

if so, proceeding to step (f5);

otherwise, proceeding to step (f6);

(f5) restoring said data of said cluster currently in said cluster register to said flash memory;

(f6) copying said data of said cluster said logical block belonging to from said flash memory to said cluster register;

(f7) reading the data of said logical block from said cluster register;

(f8) ending;

(f9) determining whether the cluster said logical block belonging to is currently in said cluster register;

if so, proceeding to step (f13);

otherwise, proceeding to step (f10);

(f10) determining whether the data of said cluster currently in said cluster register have been modified;

if so, proceeding to step (f11);

otherwise, proceeding to step (f12);

(f11) restoring said data of said cluster currently in said cluster register to said flash memory;

(f12) copying said data of said cluster said logical block belonging to from said flash memory to said cluster register;

(f13) writing said data of said logical block to said cluster register;

(f14) determining whether said write request is the last write request in the request queue;

if so, proceeding to step (f15);

otherwise, proceeding to step (f8); and

(f15) restoring said data of said cluster currently in said cluster register to said flash memory and returning to step (f8).

6. The method as claimed in claim 5, wherein step (f6) and step (f12) further comprise the following steps:

(f6a) searching for the most recent and valid data of said cluster in said flash memory;

(f6b) determining whether said data is found;

if so, proceeding to step (f6c);

otherwise proceeding to step (f6d);

(f6c) copying said data to said cluster register; and

(f6d) setting all the bits of said cluster register to 0.

7. The method as claimed in claim 5, wherein step (f5), step (f11) and step (f15) further comprise the following steps:

(f15a) determining whether said cluster is existent;

if so, proceeding to step (f15b);

otherwise, proceeding to step (f15c);

(f15b) setting said data in said cluster as invalid;

(f15c) using said free segment table to find a segment of said area said cluster belonging to having at least a free frame;

(f15d) finding a free frame in said segment;

(f15e) determining whether said free frame is found;

if so, proceeding to step (f15i);

otherwise, proceeding to step (f15f);

(f15f) finding a segment of said area said cluster belonging to having at least a free frame;

(f15g) determining whether said segment is found;

if so, proceeding to step (f15i);

otherwise, proceeding to step (f15h);

(f15h) performing garbage collection to obtain a segment having at least a free frame; and

(f15i) writing said data in said cluster register to said free frame.