System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding

• US 7,461,286 B2
• Filed: 05/11/2006
• Issued: 12/02/2008
• Est. Priority Date: 10/27/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: James, Ralph
• Primary Examiner(s): Patel; Nitin C.
• Application Number:
  US11/433,181
• Publication Number:
  US 20060206742A1
• Time in Patent Office: 936 Days
• Field of Search: 713/500, 713/503, 713/600
• US Class Current: 713/503
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: Y10S 370/905 Asynchronous transfer mode, ASN

Abstract

A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data bus and a transmitter coupled to the downstream data bus. Similarly, each of the memory modules includes a receiver coupled to the downstream data bus and a transmitter coupled to the upstream data bus. Each receiver includes a receive clock generator that is synchronized by coupling a known pattern of data to the receiver. The receiver determines which phase of the receive clock best captures the known pattern and uses that receive clock phase during normal operation.

Claims

1. A memory system comprising:

a reference clock generator operable to generate a reference clock signal;

a first memory module coupled to the reference clock generator, the first memory module operable to generate an internal clock signal based at least in part on the reference clock signal;

a second memory module coupled to the reference clock generator and operable to generate an internal clock signal based at least in part on the reference clock signal, the second memory module being coupled to the first memory module, the second memory module operable to transmit data to the first memory module and to receive data from the first memory module; and

wherein the first and second memory modules each comprises a receiver comprising;

a phase adjustment circuit configured to receive data and a predetermined pattern of data, and operable to compare the received data and the predetermined pattern of data to adjust a phase of its internal clock signal based on the comparison to generate a receive clock signal; and

a capture circuit coupled to receive the receive clock signal from the phase adjustment circuit and the data transmitted from the other memory module, the capture circuit being operable to capture the data transmitted from the other memory module in the receiver responsive to the receive clock signal.

2. The memory system of claim 1 wherein the first memory module further comprises a plurality of memory devices coupled to the receiver.

3. The memory system of claim 2 wherein the plurality of memory devices comprises a plurality of synchronous random access memory devices.

4. The memory system of claim 1 wherein the receiver is operable to generate a second internal clock signal based at least in part on the reference clock signal, wherein either the first or second memory modules are each operable to transmit the data to the other memory module using the second internal clock signal.

5. The memory system of claim 1 wherein the second memory module further comprises a second plurality of memory devices, the data transmitted to the first memory module comprising read data originating from at least one of the second plurality of memory devices.

6. The memory system of claim 1, the data comprising a read request.

7. The memory system of claim 1, the data comprising a write request.

8. The memory system of claim 1 further comprising:

a processor; and

a bus serially coupling the processor, the first memory module, and the second module, and wherein the data is transmitted from the second module to the first module on the bus.

9. The memory system of claim 1 wherein a frequency of the reference clock signal is different from a frequency of the internal clock signal.

10. The memory system of claim 1, the first memory module further comprising:

an expected pattern memory operable to provide the predetermined pattern of data; and

a comparator coupled to the expected pattern memory and the phase adjustment circuit, the comparator operable to compare data captured at the receiver with data stored in the expected pattern memory and generate a comparison signal, the phase adjustment circuit operable to adjust the phase of the internal clock signal responsive to the comparison signal.

11. The memory system of claim 1 wherein the first memory module is operable to generate a second internal clock signal based at least in part on the reference clock signal.

12. The memory system of claim 11 wherein the first memory module further comprises a transmitter operable to transmit data utilizing the second internal clock signal.

13. A method for managing asynchronous communication between a first and a second memory module, the method comprising:

receiving a reference clock signal at the first memory module;

generating a receive clock signal in the first memory module, the receive clock signal having a phase that is different from a phase of the reference clock signal;

receiving a data pattern to match to a predetermined pattern of data;

incrementally adjusting the phase of the receive clock signal based on the received data pattern matching the predetermined pattern of data; and

utilizing the receive clock signal to strobe data into the first memory module.

14. The method according to claim 13 wherein the data is transmitted to the first memory module by the second memory module utilizing a second internal clock signal generated by the second memory module.

15. The method according to claim 13 wherein a frequency of the reference clock signal is different from a frequency of the receive clock signal.

16. The method according to claim 13 wherein the act of generating the receive clock signal comprises generating an internal clock signal having a different frequency than the reference clock signal and adjusting a phase of the internal clock signal to generate the receive clock signal.

17. The method according to claim 16 further comprising:

determining a phase adjustment; and

applying the phase adjustment to the internal clock signal to generate the receive clock signal.

18. The method according to claim 17 wherein the act of determining a phase adjustment comprises identifying a left edge of a data valid eye at the receiver.

19. The method according to claim 17 wherein the act of determining a phase adjustment comprises identifying a right edge of a data valid eye at the receiver.

20. The method according to claim 17 wherein the act of determining a phase adjustment comprises identifying a left and a right edge of a data valid eye at the receiver and setting the phase adjustment equal to a value between a left phase shift corresponding to the left edge of the data valid eye and a right phase shift corresponding to the right edge of the data valid eye.

21. The method according to claim 20 wherein the phase adjustment is midway between the left phase shift and the right phase shift.

22. A memory module configured to receive data and operable to generate an internal clock signal responsive to a received reference clock signal, the memory module comprising:

a plurality of memory devices; and

a receiver coupled to the memory devices, the receiver comprising;

a phase adjustment circuit configured to receive the receive data and a predetermined pattern of data, and operable to compare the receive data to the predetermined pattern of data and adjust a phase of the internal clock signal based on the comparision to generate a receive clock signal; and

a capture circuit coupled to receive the receive clock signal from the phase adjustment circuit and data transmitted to the memory module, the capture circuit being operable to capture data in the receiver responsive to the receive clock signal.

23. The memory module of claim 22 wherein the plurality of memory devices comprises a plurality of synchronous random access memory devices.

24. The memory module of claim 22 wherein a frequency of the reference clock signal is different from a frequency of the internal clock signal.

25. The memory module of claim 22 further comprising:

an expected pattern memory operable to provide a predetermined pattern of data; and

a comparator coupled to the expected pattern memory and the phase adjustment circuit, the comparator operable to compare data captured at the receiver with data stored in the expected pattern memory and generate a comparison signal, the phase adjustment circuit operable to adjust the phase of the internal clock signal responsive to the comparison signal.

26. The memory module of claim 22 wherein the memory module is further operable to generate a second internal clock signal based at least in part on the reference clock signal.

27. The memory module of claim 26 wherein the memory module further comprises a transmitter operable to transmit data utilizing the second internal clock signal.

28. The memory module of claim 22 further comprising a second receiver, the first receiver coupleable to a downstream bus and the second receiver coupleable to an upstream bus.

29. The memory module of claim 22 further comprising a memory hub coupled to the plurality of memory devices and the receiver.