Liquid crystal display and method of manufacturing the same

• US 7,462,516 B2
• Filed: 05/27/2005
• Issued: 12/09/2008
• Est. Priority Date: 03/05/1997
• Status: Expired due to Fees

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ahn, Byung Chul
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): BARNES, SETH W
• Application Number:
  US11/138,897
• Publication Number:
  US 20050282303A1
• Time in Patent Office: 1,292 Days
• Field of Search: 438/149, 438/30, 438/652, 438/656, 438/688, 349/43, 349/46, 349/152, 257/59, 257/72, 257/347, 257/503
• US Class Current: 438/149
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14687 Wafer level processing

Abstract

The present invention relates to a method for keeping contact resistance of a pad low. The present invention also discloses a structure of the pad and a method for manufacturing the same, for use in circuit boards and LCD displays. The pad terminal comprises a first metal layer and a second metal layer covering the first metal layer. The second metal layer is removed before the pad terminal is deposited. Thus, the surface of the pad is clean and contact resistance is kept low, because there are no contaminants on the pad. Furthermore, the present invention discloses a pad having a raised part and a depressed part, enlarging the contact area of the pad. Therefore, contact resistance is reduced, and adhesion between the pad and the pad terminal is enhanced.

Claims

1. A method for manufacturing a pad terminal for a semiconductor device comprising the steps of:

forming a first pad on a substrate using a first metal;

forming a second pad covering the first pad using a second metal;

forming a protection layer over the second pad;

forming a plurality of pad contact holes over the second pad through the protection layer exposing a plurality of exposed portions of a surface of the second pad;

removing the plurality of exposed portions of the second pad using the plurality of pad contact holes as a mask thereby exposing a plurality of exposed portions of the first pad; and

forming a pad terminal comprising a conductive material and connected to the plurality of exposed portions of the first pad and a plurality of sides of the second pad through the plurality of contact holes,

wherein the step of removing the plurality of exposed portions of the second pad is separate from the step of forming the plurality of pad contact holes.

2. The method according to claim 1, wherein the conductive material comprises indium tin oxide.

3. The method according to claim 1, further comprising a step of forming a gate insulation layer after the step of forming the second pad.

5. The method according to claim 1, wherein the step of removing the plurality of exposed portions of the second pad uses wet etching.

4. A method for manufacturing a pad terminal for a semiconductor device comprising the steps of:

forming a first pad on a substrate using a first metal;

forming a second pad covering the first pad using a second metal;

forming a protection layer over the second pad;

forming a plurality of pad contact holes over the second pad through the protection layer exposing a plurality of exposed portions of the second pad;

removing the plurality of exposed portions of the second pad using the plurality of pad contact holes as a mask thereby exposing a plurality of exposed portions of the first pad; and

forming a pad terminal comprising a conductive material and connected to the plurality of exposed portions of the first pad and a plurality of sides of the second pad through the plurality of contact holes,

wherein the step of removing the plurality of exposed portions of the second pad uses dry etching.

6. A method for manufacturing a semiconductor display device comprising the steps of:

forming a gate line, a gate pad, and a gate electrode on a substrate, wherein the gate pad is located at an end portion of the gate line, wherein the gate line, the gate pad and the gate electrode includes a first metal layer and a second metal layer over the first metal layer;

forming a gate insulation layer over the substrate, the gate line, the gate pad and the gate electrode;

forming a first semiconductor layer over a gate region;

forming a doped semiconductor layer over the first semiconductor layer;

forming a source electrode over a first portion of the doped semiconductor, a drain electrode over a second portion of the doped semiconductor layer, a source pad and a source line, wherein the source pad is located at an end portion of the source line;

removing a part of the doped semiconductor layer over the gate electrode;

forming a protection layer;

patterning the protection layer forming a plurality of holes over the gate pad to expose a plurality of portions of a surface of the gate pad, a hole over the source pad to expose a portion of a surface of the source pad, and a hole over the drain electrode to expose a portion of the drain electrode;

removing the second metal layer of the plurality of exposed portions of the gate pad using the patterned protection layer as a mask thereby exposing a plurality of exposed portions of the first metal layer of the gate pad; and

forming a pixel electrode connected to the portion of the drain electrode, a gate pad terminal connected to the plurality of portions of the gate pad and a source pad terminal connected to the portion of the source pad, wherein the gate pad terminal connected to the plurality of exposed portions of the first metal layer and a plurality of sides of the second metal layer through the plurality of contact holes.

7. The method according to claim 6, wherein the gate line, the gate pad and the gate electrode comprise a bottom layer and a top layer.

8. The method according to claim 7, wherein the top layer covers the bottom layer partially.

9. The method according to claim 6, wherein the gate insulation layer comprises an insulator selected from a group consisting of silicon oxide and silicon nitride.

10. The method according to claim 6, wherein the source pad, the source line, the source electrode, and the drain electrode comprise chromium.

11. The method according to claim 6, wherein the pixel electrode, the gate pad terminal, and the source pad terminal comprise indium tin oxide.

12. The method according to claim 6, wherein the protection layer comprises an insulator selected from a group consisting of silicon oxide and silicon nitride.

13. The method according to claim 7, wherein the step of patterning the protection layer uses dry etching, and results in the gate pad terminal being connected to the bottom layer.

14. The method according to claim 7, wherein the step of patterning the protection layer uses wet etching, and results in the gate pad terminal being connected to the bottom layer.