Manufacturing method of semiconductor device

• US 7,462,541 B2
• Filed: 10/17/2005
• Issued: 12/09/2008
• Est. Priority Date: 06/11/2003
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Izumisawa, Masaru, Yoshioka, Hironori, Kouzuki, Shigeo, Aida, Satoshi
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): Kim; Su C
• Application Number:
  US11/250,464
• Publication Number:
  US 20060049459A1
• Time in Patent Office: 1,149 Days
• Field of Search: 438/268, 438/270, 438/271, 438/272, 438/561, 438/142, 438/197, 438/259, 257/341, 257/339, 257/342
• US Class Current: 438/270
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminating portion side.

Claims

1. A manufacturing method of a semiconductor device comprising:

forming a drift layer of a first conductivity type on a first main surface of a semiconductor substrate of a first conductivity type, a surface of the drift layer having a first area for a cell portion and a second area for a terminating portion which is positioned on an outer periphery of the first area and alleviates an electric field to maintain a breakdown voltage by extending a depletion layer;

forming a first insulating film with a first thickness in the second area on the drift layer;

forming a base layer by implanting a second conductivity type impurity into the drift layer and then diffusing it by a heat treatment;

selectively forming an impurity diffused layer in a surface layer of the base layer in the second area by implanting a second conductivity type impurity into the base layer by using a resist and then diffusing it by a heat treatment, the impurity diffused layer having first and second opposing end surfaces, the first end surface being located closer to the first area than the second end surface;

selectively forming a source layer of a first conductivity type in a surface layer of the base layer in the first area;

forming a trench which reaches the drift layer from a surface of the source layer through the base layer and forming a second insulating film on a bottom surface and side surfaces of the trench;

forming a control electrode by filling the trench via the second insulating film with an electrode material; and

forming a first metallic compound and a second metallic compound to surface layers of the source layer and of the control electrode, respectively, by depositing a metallic material on the source layer, the control electrode and the impurity diffused layer, causing the source layer, the control electrode and the impurity diffused layer to react with the metallic material by a heat treatment and then selectively removing the metallic material, and forming a third metallic compound to a surface layer of the impurity diffused layer, the third metallic compound having third and fourth opposing end surfaces, the third end surface being located closer to the first area than the fourth end surface, and the fourth end surface being spaced from the second end surface on an upper surface of the impurity diffused region by a distance.

2. The manufacturing method of a semiconductor device according to claim 1, further comprising forming a first side wall spacer on an end surface of the first insulating film on the cell portion side after forming the impurity diffused layer and before forming the first through third metallic compounds,

wherein the third metallic compound is formed in a self-alignment manner using the first side wall spacer as a mask.

3. The manufacturing method of a semiconductor device according to claim 1, wherein the impurity diffused layer is formed in a self-alignment manner with an end portion of the first insulating film being used as a mask.

4. The manufacturing method of a semiconductor device according to claim 2, wherein forming the first side wall spacer includes forming a second side wall spacer on side surfaces of the control electrode, and

the second metallic compound is formed so as to extend onto a top face of the second side wall spacer.

5. The manufacturing method of a semiconductor device according to claim 2, wherein the control electrode is formed in such a manner that a top face thereof protrudes from a top face of the source layer,

forming the first side wall spacer includes forming a second side wall spacer on side surfaces of the control electrode, and

the second metallic compound is formed so as to extend onto an upper surface of the second side wall spacer.

6. The manufacturing method of a semiconductor device according to claim 2, wherein the control electrode is formed in the trench in such a manner that its top face becomes lower than a surface of the source layer,

forming the first side wall spacer includes forming a second side wall spacer on side surfaces of the second insulating film, and

the second metallic compound is formed so as to be sandwiched by the second side wall spacer.

7. The manufacturing method of a semiconductor device according to claim 1, further comprising forming a third insulating film having a thickness which allows passage of a second conductivity impurity for forming the impurity diffused layer on a surface of an area on the terminating portion side in an area where the impurity diffused layer is formed,

wherein the impurity diffused layer is formed in a self-alignment manner using the third insulating film as a mask.

8. The manufacturing method of a semiconductor device according to claim 1, wherein the third metallic compound is formed in such a manner that the distance is 0.2 μ

m or more.

9. The manufacturing method of a semiconductor device according to claim 1, further comprising forming a field plate electrode on the first insulating film.

10. The manufacturing method of a semiconductor device according to claim 9, wherein forming the first through third metallic compounds includes forming a fourth metallic compound in a surface layer of the field plate electrode.

11. The manufacturing method of a semiconductor device according to claim 9, wherein the control electrode and the field plate electrode are simultaneously formed.