Transistor using an isovalent semiconductor oxide as the active channel layer

• US 7,462,862 B2
• Filed: 10/25/2005
• Issued: 12/09/2008
• Est. Priority Date: 03/12/2004
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Hoffman, Randy L., Herman, Gregory S.
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US11/257,935
• Publication Number:
  US 20060043377A1
• Time in Patent Office: 1,141 Days
• Field of Search: 257/20, 257/22, 257/43, 257/E29.299
• US Class Current: 257/43
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A semiconductor device can include a channel including an oxide comprising a combination of isovalent cations selected from within the D block and the P block of the Periodic Table.

Claims

1. A semiconductor device, comprising:

a drain electrode;

a source electrode;

means for a channel to electrically couple the drain electrode and the source electrode, the means comprising an isovalent semiconductor film including indium gallium oxide;

a gate electrode; and

a gate dielectric positioned between the gate electrode and the channel.

2. A display device, comprising:

a plurality of display elements configured to operate collectively to display images, where each of the display elements includes a semiconductor device configured to control light emitted by the display element, the semiconductor device including;

a drain electrode;

a source electrode;

an isovalent semiconductor channel contacting the drain electrode and the source electrode, wherein the channel includes an oxide comprising a combination of isovalent cations selected from within the P block of the Periodic Table;

a gate electrode; and

a gate dielectric positioned between the gate electrode and the channel and configured to permit application of an electric field to the channel.

3. A semiconductor device, comprising:

a drain electrode;

a source electrode;

a channel contacting the drain electrode and the source electrode, wherein the channel includes an oxide comprising a combination of isovalent cations selected from within the D block and the P block of the Periodic Table;

a gate electrode; and

a gate dielectric positioned between the gate electrode and the channel;

wherein the combination comprises indium gallium oxide and wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) of greater than about 0.5.

4. A semiconductor device, comprising:

a drain electrode;

a source electrode;

a channel contacting the drain electrode and the source electrode, wherein the channel includes an oxide comprising a combination of isovalent cations selected from within the D block and the P block of the Periodic Table;

a gate electrode; and

a gate dielectric positioned between the gate electrode and the channel;

wherein the combination is selected from a group consisting of;

tin titanium oxide;

tin germanium oxide; and

tin titanium germanium oxide.

5. A semiconductor device, comprising:

a drain electrode;

a source electrode;

a channel contacting the drain electrode and the source electrode, wherein the channel includes an oxide comprising a combination of isovalent cahions selected from within the D block and the P block of the Periodic Table;

a gate electrode; and

a gate dielectric positioned between the gate electrode and the channel, wherein the combination comprises tin oxide and a second 4⁺ cation selected from within the D block and the P block of the Periodic Table.

6. The semiconductor device of claim 5, wherein the combination is selected from a group consisting of:

tin titanium oxide;

tin germanium oxide; and

tin titanium germanium oxide.

7. A semiconductor device, comprising:

a drain electrode;

a source electrode;

an isovalent semiconductor channel contacting the drain electrode and the source electrode, wherein the channel includes an oxide-comprising a combination of isovalent cations selected from within the D block and the P block of the Periodic Table and wherein the combination comprises indium gallium oxide;

a gate electrode; and

a gate dielectric positioned between the gate electrode and the channel.

8. The semiconductor device of claim 7, wherein the channel has a peak incremental channel mobility of at least about 40 cm²/V s with a turn-on voltage greater than or equal to about −

15 volts.

9. The semiconductor device of claim 7, wherein the channel has a peak incremental channel mobility of at least about 2 cm²/V s and a turn-on voltage of between about −

5 volts and +5 volts.

10. The semiconductor device of claim 7, wherein the indium gallium oxide is sputter deposited.

11. The semiconductor device of claim 7, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) of greater than about 0.5.

12. The semiconductor device of claim 7, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) in a range of about 0.1 to about 0.5.

13. The semiconductor device of claim 7, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) of about 0.9.

14. The semiconductor device of claim 7, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) in a range of about 0.25 to about 0.35.

15. The semiconductor device of claim 7, wherein the indium gallium oxide has an atomic ratio of In(In+Ga) in a range of about 0.05 to about 0.95.

16. A semiconductor device, comprising:

a drain electrode;

a source electrode;

an isovalent semiconductor channel contacting the drain electrode and the source electrode, wherein the channel includes an oxide-comprising a combination of isovalent cations selected from within the P block of the Periodic Table;

a gate electrode; and

a gate dielectric positioned between the gate electrode and the channel.

17. The semiconductor device of claim 16, wherein the channel includes one of an amorphous form, a single-phase crystalline form, and a mixed- phase crystalline form.

18. The semiconductor device of claim 16, wherein at least one of the drain electrode, the source electrode, the channel, the gate electrode, and the gate dielectric are substantially transparent.

19. The semiconductor device of claim 16, wherein the channel is substantially transparent.

20. The semiconductor device of claim 16, wherein the combination comprises tin oxide and a second 4⁺ cation selected from within the D block and the P block of the Periodic Table.

21. The semiconductor device of claim 16, wherein the combination is selected from a group consisting of:

tin titanium oxide;

tin germanium oxide; and

tin titanium germanium oxide.

22. The semiconductor device of claim 16, wherein the combination comprises indium gallium oxide.

23. The semiconductor device of claim 22, wherein the channel has a peak incremental channel mobility of at least about 40 cm²/V s with a turn-on voltage greater than or equal to about −

15 volts.

24. The semiconductor device of claim 22, wherein the channel has a peak incremental channel mobility of at least about 2 cm²/V s and a turn-on voltage of between about −

5 volts and +5 volts.

25. The semiconductor device of claim 22, wherein the indium gallium oxide is sputter deposited.

26. The semiconductor device of claim 22, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) of greater than about 0.5.

27. The semiconductor device of claim 22, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) in a range of about 0.1 to about 0.5.

28. The semiconductor device of claim 22, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) of about 0.9.

29. The semiconductor device of claim 22, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) in a range of about 0.25to about 0.35.

30. The semiconductor device of claim 22, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) in a range of about 0.05 to about 0.95.