Semiconductor device having an interconnect with sloped walls and method of forming the same
First Claim
1. A semiconductor device, comprising:
- a substrate having a source contact covering a substantial portion of a bottom surface thereof;
a first buffer layer formed over said substrate;
an isolation layer formed over said first buffer layer;
a first spacer layer formed over said isolation layer;
a second buffer layer formed over said first spacer layer;
a first barrier layer formed over said second buffer layer;
a second spacer layer formed over said first barrier layer;
a first lateral channel formed over said second spacer layer;
a third spacer layer formed over said first lateral channel;
a fourth spacer layer formed over said third spacer layer;
a second lateral channel formed over said fourth spacer layer;
a fifth spacer layer formed over said second lateral channel;
a sixth spacer layer formed over said fifth spacer layer;
a third lateral channel formed over said sixth spacer layer;
a seventh spacer layer formed over said third lateral channel;
a second barrier layer formed over said seventh spacer layer;
a recess layer formed over said second barrier layer;
an etch-stop layer formed over said recess layer;
first and second source/drain contact layers formed over said etch-stop layer;
a source interconnect having a sloped wall that connects said first, second and third lateral channels to said substrate operable to provide a low resistance coupling between said source contact and said first, second and third lateral channels;
a gate located in a gate recess formed though said first and second source/drain contact layers, said etch-stop and said recess layer;
a dielectric layer formed over said gate, and said first and second source/drain contact layers;
a drain post located in a drain via formed through said dielectric layer and over said first and second source/drain contact layers; and
a drain contact coupled to said drain post.
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Accused Products
Abstract
A semiconductor device having at least one lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a lateral channel above the conductive substrate. The semiconductor device further includes a second contact above the lateral channel. The semiconductor device still further includes an interconnect having a sloped wall that connects the lateral channel to the conductive substrate. The interconnect is operable to provide a low resistance coupling between the first contact and the lateral channel. In a related but alternative embodiment, the first contact is a source contact and the second contact is a drain contact for the semiconductor device.
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Citations
20 Claims
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1. A semiconductor device, comprising:
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a substrate having a source contact covering a substantial portion of a bottom surface thereof; a first buffer layer formed over said substrate; an isolation layer formed over said first buffer layer; a first spacer layer formed over said isolation layer; a second buffer layer formed over said first spacer layer; a first barrier layer formed over said second buffer layer; a second spacer layer formed over said first barrier layer; a first lateral channel formed over said second spacer layer; a third spacer layer formed over said first lateral channel; a fourth spacer layer formed over said third spacer layer; a second lateral channel formed over said fourth spacer layer; a fifth spacer layer formed over said second lateral channel; a sixth spacer layer formed over said fifth spacer layer; a third lateral channel formed over said sixth spacer layer; a seventh spacer layer formed over said third lateral channel; a second barrier layer formed over said seventh spacer layer; a recess layer formed over said second barrier layer; an etch-stop layer formed over said recess layer; first and second source/drain contact layers formed over said etch-stop layer; a source interconnect having a sloped wall that connects said first, second and third lateral channels to said substrate operable to provide a low resistance coupling between said source contact and said first, second and third lateral channels; a gate located in a gate recess formed though said first and second source/drain contact layers, said etch-stop and said recess layer; a dielectric layer formed over said gate, and said first and second source/drain contact layers; a drain post located in a drain via formed through said dielectric layer and over said first and second source/drain contact layers; and a drain contact coupled to said drain post. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification