Dynamic deep depletion field effect transistor

• US 7,462,908 B2
• Filed: 07/14/2005
• Issued: 12/09/2008
• Est. Priority Date: 07/14/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Bol, Igor, Li, Xin
• Primary Examiner(s): Wojciechowicz; Edward
• Application Number:
  US11/181,292
• Publication Number:
  US 20060017100A1
• Time in Patent Office: 1,244 Days
• Field of Search: 257/328, 257/330, 257/331
• US Class Current: 257/328
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A vertical conduction trench FET has a plurality of trenches containing conductive polysilicon gates. The mesas between the trenches have a source diffusion region connected to a common source electrode. The trenches are spaced so that the depletion regions induced by the trench gate will overlap to pinch off conduction through the mesa to turn off the device. The gate potential is pulsed. The polysilicon in the trenches may be separated into two insulated portions. The pulses may be applied simultaneously or sequentially to the polysilicon gates.

Claims

1. A semiconductor switching device comprising a semiconductor die of only one conductivity type formed over a substrate of said one conductivity type and having a plurality of equally spaced trenches, each pair of said trenches including a depletable region of only one conductivity type therebetween;

a gate insulation lining at least a portion of the walls of said trenches;

a conductive polysilicon mass disposed within each said trench for a height from the bottom of said trench;

a source region of said one conductivity type but lower resistivity than said semiconductor die atop each depletable region;

a source contact disposed in contact with said source regions and insulated from said conductive polysilicon masses;

said polysilicon masses being connectable to a source of gate to source bias to receive pulse voltages;

wherein said width and conductivity of said depletable regions are configured such that said depletion regions are generated around each trench and overlap one another inside each depletable region to deplete said depletable regions when said pulse voltages are applied to said polysilicon masses.

2. The device of claim 1, wherein said mesa regions have a doping level of about 2E16/cm² and wherein said pulse volatages create said depletion regions in the order of 10s of milliseconds after the application of a pulse.

3. The device of claim 1, wherein said mesas have a width that is optimized for the selected channel doping level.

4. The device of claim 3, wherein said trenches have a width of about 0.3 to 0.5 microns.

5. The device of claim 3, wherein said pulse voltages are in the range of 4 to 10 volts.

6. The switching device of claim 1, wherein each said polysilicon mass is divided into first and second insulated masses.

7. The device of claim 1, wherein said pulse voltages are provided simultaneously.

8. The device of claim 3, wherein said pulse voltages are provided alternately.