Method and apparatus for increase strain effect in a transistor channel

• US 7,462,915 B2
• Filed: 08/25/2006
• Issued: 12/09/2008
• Est. Priority Date: 01/16/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Zhu, Huilong
• Primary Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US11/467,446
• Publication Number:
  US 20060286786A1
• Time in Patent Office: 837 Days
• Field of Search: 257/411, 257/366, 257/635, 257/288, 257/E29.156, 257/E29.16, 257/E29.161
• US Class Current: 257/369
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

A semiconductor device having a transistor channel with an enhanced stress is provided. To achieve the enhanced stress transistor channel, a nitride film is preferentially formed on the device substrate with little to no nitride on a portion of the gate stack. The nitride film may be preferentially deposited only on the silicon substrate in a non-conformal layer, where little to no nitride is deposited on the upper portions of the gate stack. The nitride film may also be uniformly deposited on the silicon substrate and gate stack in a conformal layer, with the nitride film proximate the upper regions of the gate stack preferentially removed in a later step. In some embodiments, nitride near the top of the gate stack is removed by removing the upper portion of the gate stack. In any of the methods, stress in the transistor channel is enhanced by minimizing nitride deposited on the gate stack, while having nitride deposited on the substrate.

Claims

1. A semiconductor device, comprising:

a silicon substrate;

a gate stack disposed on the silicon substrate; and

a stressed nitride film on the silicon substrate and the gate stack, wherein the stressed nitride film comprises a thicker portion deposited on the silicon substrate and a thinner portion deposited on a portion of the gate stack.

2. The semiconductor device of claim 1, further comprising spacers disposed on the substrate between the stressed nitride film and the gate stack leaving an upper portion of the gate stack exposed.

3. The semiconductor device of claim 1, further comprising a salicide gate region formed on a top of the gate stack.

4. The semiconductor device of claim 1, wherein the nitride film is thicker over a surface of the substrate and thinner over the portion of the gate stack.

5. The semiconductor device of claim 1, wherein a gate is about 60 nm wide and a spacer is about 50 nm wide

6. The semiconductor device of claim 5, wherein the stressed nitride film provides a stress of about 2.0 GPa.

7. The semiconductor device of claim 6, wherein an enhanced stress in a transistor channel is greater than approximately 4.5×

10⁹ dynes/cm² at about 5 nm below a gate oxide.

8. A semiconductor device, comprising:

a silicon substrate;

a gate stack disposed on the silicon substrate;

a stressed nitride film on the silicon substrate and the gate stack, wherein the stressed nitride film is thicker over the silicon substrate and thinner over a portion of the gate stack, wherein the stressed nitride film is substantially absent in the upper portion of the gate stack.

9. The semiconductor device of claim 8, further comprising only a lower portion of the gate stack.

10. The semiconductor device of claim 9, further comprising a spin-on material disposed over the stressed nitride film leaving the gate stack exposed.

11. A semiconductor device, comprising:

a silicon substrate;

a gate stack disposed on the silicon substrate;

a stressed nitride film on the silicon substrate and the gate stack, wherein the stressed nitride film is thicker over the silicon substrate and thinner over a portion of the gate stack, wherein a spacer is adjacent only a lower portion of the gate stack.

12. The semiconductor device of claim 11, wherein the spacer comprises reducing a size of the spacer.

13. A semiconductor device, comprising:

a silicon substrate;

a gate stack disposed on the silicon substrate;

a stressed nitride film on the silicon substrate and the gate stack, wherein the stressed nitride film is thicker over the silicon substrate and thinner over a portion of the gate stack, wherein the stressed nitride film is a non-conformal nitride film.

14. A semiconductor device, comprising

a silicon substrate with a gate oxide thereon;

a gate stack with gate sidewalls is located on the gate oxide;

a gate salicide region formed on top of the gate stack;

a nitride film on a surface of the silicon substrate;

a stressed transistor channel formed within the silicon substrate; and

a salicide gate region formed on the top of the gate stack.

15. A semiconductor device, comprising:

a silicon substrate with a gate oxide thereon;

a gate stack with gate sidewalls is located on the gate oxide;

a gate salicide region formed on top of the gate stack;

a nitride film on a surface of the silicon substrate;

a stressed transistor channel formed within the silicon substrate; and

a salicide gate region formed on the top of the gate stack,

wherein an upper portion of the gate stack is substantially devoid of the nitride film.