Structured integrated circuit device

• US 7,463,062 B2
• Filed: 04/24/2007
• Issued: 12/09/2008
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi, Levinthal, Adam, Wurman, Ze'ev, Mihelcic, Stan, Cooke, Laurence
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US11/739,538
• Publication Number:
  US 20070188188A1
• Time in Patent Office: 595 Days
• Field of Search: 326/37, 326/41, 326/47, 326/93
• US Class Current: 326/41
• CPC Class Codes: H01L 2224/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.

Claims

1. A method for customizing a clock distribution system within a semiconductor device, said clock distribution system comprising at least one customizable trimmer cell to fine tune said clock distribution system'"'"'s delay, and at least one customizable phase lock loop circuit, said method comprising:

configuring phase and frequency of at least one clock by configuring at least one said phase lock loop circuit; and

customizing delay of said clock distribution system by customizing at least one customizable trimmer cell, said customizing including selecting one or more vias of a custom via layer.