Low power single-rail-input voltage level shifter

• US 7,463,065 B1
• Filed: 11/13/2006
• Issued: 12/09/2008
• Est. Priority Date: 11/13/2006
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Yang, Ge, Young, Charles Chew-Yuen, Lin, Hwong-Kwo
• Primary Examiner(s): Barnie; Rexford
• Assistant Examiner(s): Tran; Thienvu V
• Application Number:
  US11/559,155
• Time in Patent Office: 757 Days
• Field of Search: 326/62, 326/63, 326/68, 326/80, 326/81
• US Class Current: 326/68
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration

Abstract

An apparatus includes a single-rail input connected to a low-voltage domain and a voltage-transition circuit connected to the single-rail input. The voltage-transition circuit is configured to convert a voltage of the low-voltage domain received via the single-rail input to a voltage of the high-voltage domain.

Claims

1. A processor comprising a multiplicity of voltage level shifters, each voltage level shifter comprising:

a single-rail input connected to a voltage VDDL of a low-voltage domain; and

a voltage-transition circuit connected to the single-rail input, the voltage-transition circuit being configured to convert a voltage of the low-voltage domain received via the single-rail input to a voltage VDDH of a high-voltage domain,

wherein the voltage-transition circuit includes an input-falling-transition circuit comprising;

a first p-type transistor; and

a first n-type transistor having a drain connected to a drain of the first p-type transistor at a contact point, the first n-type transistor having a source connected to the single-rail input, the first n-type transistor having a gate connected to a reference voltage (VREF), the first p-type transistor having a source connected to the VDDH voltage of the high-voltage domain; and

wherein the voltage-transition circuit includes an input-rising-transition circuit comprising;

a second n-type transistor having a gate connected to the single-rail input, the second n-type transistor having a source connected to a ground voltage, the second n-type transistor having a drain connected to an output contact point, the output contact point being connected to a gate of the first p-type transistor of an input-falling-transition circuit; and

a second p-type transistor having a drain connected to the output contact point, the second p-type transistor having a gate connected to the contact point of the input-falling-transition circuit;

wherein the reference voltage is a voltage different from VDDH to permit operation in a voltage regime in which wherein both VDDH and VDDL have a nominal value no greater than about one volt such that the difference between VDDH and VDDL has a comparable magnitude to threshold voltages of said first n-type transistor and said second n-type transistor, the threshold voltage and size of said first n-type transistor being selected to permit the first n-type transistor to turn on in response to a falling voltage and turn off in response to a rising voltage and the size of the second n-type transistor being selected to permit the second n-type transistor to pull the voltage of the output contact point from VDDH to a ground voltage (GND);

wherein the threshold voltage of the first n-type transistor is greater than the difference between the reference voltage and VDDL so that the first transistor will turn off in response to a rising voltage, the second transistor has a threshold voltage less than the difference between VDDL and GND so that the second transistor will turn on in response to a rising voltage;

wherein the first n-type transistor has a threshold voltage that is less than the difference between VDDL and GND so that the first transistor will turn on in response to a falling voltage and the first transistor is sized to have the strength to pull the voltage of the contact point from VDDH to GND;

the second n-type transistor being sized to have the strength to pull the voltage of the output contact point from VDDH to GND; and

wherein the n-type transistor of each voltage level shifter is sized such that a change in a voltage of the single-rail input from a ground voltage to a VDDL voltage of the low-voltage domain triggers a voltage of the output contact point to change from a VDDH voltage of the high-voltage domain to the ground voltage.

2. The processor of claim 1, wherein the voltage-transition circuit of each voltage level shifter includes a p-type blocking transistor that prevents a substantially high current path from forming between a VDDH voltage of the high-voltage domain and a ground voltage when the voltage of the single-rail input is the VDDL voltage.

3. The processor of claim 1, wherein the VDDL voltage is the range 0.8V±

10% and the VDDH voltage is in the range 1V±

10%.

4. A processor comprising a multiplicity of voltage level shifters, each voltage level shifter comprising:

a single-rail input connected to a low voltage VDDL of a low-voltage domain; and

a voltage-transition circuit connected to the single-rail input, the voltage-transition circuit being configured to convert a voltage of the low-voltage domain received via the single-rail input to a voltage VDDH of a high-voltage domain,

wherein the voltage-transition circuit includes an input-falling-transition circuit comprising;

a first p-type transistor; and

a first n-type transistor having a drain connected to a drain of the first p-type transistor at a contact point, the first n-type transistor having a source connected to the single-rail input, the first n-type transistor having a gate connected to a reference voltage (VREF), the first p-type transistor having a source connected to the VDDH voltage of the high-voltage domain; and

wherein the voltage-transition circuit includes an input-rising-transition circuit comprising;

a second n-type transistor having a gate connected to the single-rail input, the second n-type transistor having a source connected to a ground voltage, the second n-type transistor having a drain connected to an output contact point, the output contact point being connected to a gate of the first p-type transistor of an input-falling-transition circuit; and

a second p-type transistor having a drain connected to the output contact point, the second p-type transistor having a gate connected to the contact point of the input-falling-transition circuit;

the input-falling-transition circuit triggers a voltage of the output node to change from a VDDH voltage of a high-voltage domain to a ground voltage in response to a voltage of the single-rail-input node changing from a VDDL voltage of a low-voltage domain to the ground voltage,

the input-rising-transition circuit triggers a voltage of the output node to change from the ground voltage to the VDDH voltage in response to the voltage of the single-rail-input node changing from the ground voltage to the VDDL voltage; and

wherein the reference voltage is a voltage different from VDDH to permit operation in a voltage regime in which both VDDH and VDDL have a nominal value no greater than about one volt such that the difference between VDDH and VDDL has a comparable magnitude to threshold voltages of said first n-type transistor and said second n-type transistor, the threshold voltage and size of said first n-type transistor being selected to permit the first n-type transistor to turn on in response to a falling voltage and turn off in response to a rising voltage and the size of the second n-type transistor being selected to permit the second n-type transistor to pull the voltage of the output contact point from VDDH to a ground voltage (GND)

wherein the threshold voltage of the first n-type transistor is greater than the difference between the reference voltage and VDDL so that the first transistor will turn off in response to a rising voltage, the second transistor has a threshold voltage less than the difference between VDDL and GND so that the second transistor will turn on in response to a rising voltage;

wherein the first n-type transistor has a threshold voltage that is less than the difference between VDDL and GND so that the first transistor will turn on in response to a falling voltage and the first transistor is sized to have the strength to pull the voltage of the contact point from VDDH to GND;

the second n-type transistor being sized to have the strength to pull the voltage of the output contact point from VDDH to GND; and

wherein the n-type transistor of each voltage level shifter is sized such that a change in a voltage of the single-rail input from a ground voltage to a VDDL voltage of the low-voltage domain triggers a voltage of the output contact point to change from a VDDH voltage of the high-voltage domain to the ground voltage.

5. The processor of claim 4, wherein each voltage level shifter further comprises a reference voltage input node having a voltage at the VDDL voltage.

6. The processor of claim 4, wherein each voltage level shifter has a first state and a second state, the voltage of the single-rail-input node is the ground voltage in the first state and the voltage of the output node is the ground voltage in the first state, the voltage of the single-rail-input node is the VDDL voltage in the second state and the voltage of the output node is the VDDH voltage in the second state, an operating current associated with the voltage level shifter while in the first state is substantially the same as the operating current associated with the voltage level shifter while in the second state.

7. The processor of claim 4, the input-rising-transition circuit of each voltage level shifter includes a blocking transistor that substantially reduces current flow through the input-rising-transition circuit when the voltage of the single-rail-input node is the VDDL voltage.

8. The processor of claim 4, wherein the VDDL voltage is the range 0.8V±

10% and the VDDH voltage is in the range 1V±

10%.