Series arc fault current interrupters and methods

• US 7,463,465 B2
• Filed: 12/28/2006
• Issued: 12/09/2008
• Est. Priority Date: 12/28/2006
• Status: Active Grant

• Current Assignee: ABB Schweiz AG (ABB Limited)
• Original Assignee: General Electric Company
• Inventors: Younsi, Karim, Yan, Weizhong, Zhou, Yingneng, Hu, Xiao, Dwyer, Sean, Prasad, Vijaysai, Vijayan, Pradeep, Rivers, Cecil
• Primary Examiner(s): Nguyen; Danny
• Application Number:
  US11/646,733
• Publication Number:
  US 20080158744A1
• Time in Patent Office: 712 Days
• Field of Search: 361/42, 361/44, 361/50, 702/58
• US Class Current: 361/42
• CPC Class Codes: H02H 1/0015 Using arc detectors

Abstract

A circuit interrupter for interrupting current on a line conductor is provided. The circuit interrupter includes separable contacts, a trip mechanism, a bimetal, a microprocessor, a series arc detection sequence, a low-pass filter circuit, and a high-pass filter circuit. The trip mechanism selectively opens the separable contacts when activated. The series arc detection sequence is resident on the microprocessor and includes a plurality of series fault detection algorithms. The low-pass filter circuit provides a low-pass signal to the series arc detection sequence. The high-pass filter circuit provides a high-pass signal to the series arc detection sequence. The sequence selects a particular algorithm from the plurality of algorithms based on the low-pass signal. The sequence calculates a plurality of statistical features from the high-pass signal and sends an output signal to activate the trip mechanism based on a comparison of the plurality of statistical features to the particular algorithm.

Claims

1. A circuit interrupter for interrupting current on a line conductor, comprising:

separable contacts in electrical communication with the line conductor;

a trip mechanism for selectively opening said separable contacts when activated;

a bimetal connected in series with the line conductor;

a microprocessor in electrical communication with said trip mechanism;

a series arc detection sequence resident on said microprocessor, said series arc detection sequence comprising a plurality of series fault detection algorithms;

a low-pass filter circuit configured to provide a low-pass signal from said bimetal to said series arc detection sequence, said sequence being configured to select a particular algorithm from said plurality of algorithms based on said low-pass signal; and

a high-pass filter circuit configured to provide a high-pass signal from said bimetal to said series arc detection sequence, said sequence being configured to calculate a plurality of statistical features from said high-pass signal and being configured to send an output signal to activate said trip mechanism based on a comparison of said plurality of statistical features to said particular algorithm.

2. The circuit interrupter as in claim 1, wherein said trip mechanism is configured to activate upon application of an overcurrent across said bimetal.

3. The circuit interrupter as in claim 2, wherein said trip mechanism is configured to activate upon application of a short circuit across said bimetal.

4. The circuit interrupter as in claim 3, further comprising a parallel arc detector configured to activate said trip mechanism upon detection of a parallel arc across the line conductor.

5. The circuit interrupter as in claim 1, further comprising a parallel arc detector configured to activate said trip mechanism upon detection of a parallel arc across the line conductor.

6. The circuit interrupter as in claim 1, further comprising an analog-to-digital converter for sampling said low-pass and high-pass signals from said high and low-pass filters.

7. The circuit interrupter as in claim 1, wherein said sequence is configured to calculate said plurality of statistical features from said low-pass signal and is configured to send said output signal to activate said trip mechanism based on said comparison of said plurality of statistical features to said particular algorithm.

8. The circuit interrupter as in claim 1, wherein said low-pass filter circuit further comprises a DC offset.

9. The circuit interrupter as in claim 1, wherein said high-pass filter circuit further comprises an amplifier and a DC offset.

10. A method for detecting a series arc fault on a line conductor, comprising:

sensing current across a bimetal in series with the line conductor;

passing said current through a high-pass filter circuit to generate a high-pass signal;

passing said current through a low-pass filter circuit to generate a low-pass signal;

calculating a plurality of statistical features based at least on said high-pass signal;

selecting a particular arc series algorithm from a plurality of algorithms based on said low-pass signal; and

determining a trip command based on said plurality of statistical features and said particular arc series algorithm.

11. The method as in claim 10, further comprising calculating said plurality of statistical features based on said low-pass signal.

12. The method as in claim 11, further comprising digitally filtering said low-pass signal through a 10-pole rectangular band-pass digital filter from between about 700 to about 3000 Hz.

13. The method as in claim 12, wherein said plurality of statistical features calculated based on said low-pass signal are selected from the group consisting of a standard deviation of the difference between adjacent points in a cycle, an approximation of the standard deviation of a difference between adjacent points in a cycle, a mean of the difference between adjacent points, and any combinations thereof.

14. The method as in claim 11, wherein said plurality of statistical features are selected from the group consisting of a mean of a full cycle, a standard deviation of said full cycle, a maximum standard deviation of any window in said full cycle, a minimum standard deviation of any window in said full cycle, a ratio of said maximum and minimum standard deviations, an absolute sum of each sample in said full cycle, a relation of said maximum and minimum standard deviations for each adjacent window in said full cycle, an RMS value, and any combinations thereof.

15. The method as in claim 11, wherein said plurality of statistical features are selected from the group consisting of a maximum difference between two adjacent samples, a minimum difference between said two adjacent samples, a ratio of said maximum difference to said minimum difference, a range of said maximum difference to said minimum difference, a sum of said maximum and minimum differences between adjacent points, and any combinations thereof.

16. The method as in claim 15, wherein said plurality of statistical features are selected from the group consisting of a second difference signal, a difference between adjacent points in a first difference signal, a maximum difference between two adjacent samples, a minimum difference between two adjacent samples, ratio of said maximum difference to said minimum difference, a range of said maximum difference minus said minimum difference, a sum of differences between adjacent points, and any combinations thereof.

17. The method as in claim 11, wherein said plurality of statistical features are selected from the group consisting of a number of distinct peaks in said high-pass signal that occur while said low-pass signal is negative.