Distributed direct memory access for systems on chip

• US 7,464,197 B2
• Filed: 01/14/2005
• Issued: 12/09/2008
• Est. Priority Date: 09/08/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ganapathy, Kumar, Kanapathippillai, Ruban, Moussa, George, Philhower, Earle F. III, Shah, Saurin, Shah, Ruchir
• Primary Examiner(s): Chen; Alan S
• Application Number:
  US11/036,828
• Publication Number:
  US 20050125572A1
• Time in Patent Office: 1,425 Days
• Field of Search: None
• US Class Current: 710/22
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2213/0038 System on Chip
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Claims

1. An apparatus comprising:

a system on a chip including

a buffer memory;

a system bus coupled to the buffer memory;

a plurality of bus arbitrators coupled to the system bus; and

a plurality of functional modules coupled to the plurality of bus arbitrators,

each of the plurality of functional modules including

a direct memory access (DMA) controller to couple to a bus arbitrator of the plurality of bus arbitrators, the DMA controller to provide direct memory access to the buffer memory, and

a processor coupled to the DMA controller;

wherein each bus arbitrator is coupled between a direct memory access controller and the system bus to provide access to the system bus for the direct memory access controller.

2. The apparatus of claim 1, wherein the plurality of bus arbitrators negotiate access to the system bus by the plurality of functional modules.

3. The apparatus of claim 1, wherein the system on a chip further includes a microcontroller coupled to the system bus.

4. The apparatus of claim 1, wherein the buffer memory is a global memory and includes a direct memory access controller.

5. The apparatus of claim 4, wherein the system bus includes

a data bus over which data can flow between the global memory and the plurality of functional modules, and

DMA control lines to request direct memory access to the global memory and control the direct memory data flow with the global memory.

6. The apparatus of claim 4, wherein the direct memory access controller of the global memory includes

a receive first in first out (FIFO) buffer to store receive data,

a transmit first in first out (FIFO) buffer to store and transmit data,

a data counter to count a number of data units that were transmitted to the memory and received from the memory by direct memory access, and

control logic coupled to the receive FIFO buffer, the transmit FIFO buffer, and

the data counter to control the transmission and reception of data by direct memory access.

7. The apparatus of claim 6, wherein the DMA controller in each of the plurality of functional modules includes

a receive first in first out (FIFO) buffer to store receive data,

a transmit first in first out (FIFO) buffer to store transmit data,

a data counter to count a number of data units that were transmitted to the memory and received from the global memory by direct memory access, and

control logic coupled to the receive FIFO buffer, the transmit FIFO buffer, and

the data counter to control the transmission and reception of data by direct memory access.

8. The apparatus of claim 7, wherein the DMA controller in at least one of the functional modules further includes a remapper memory to remap parallel data into serial data and serial data into parallel data.

9. The apparatus of claim 1, wherein the buffer memory includes

a descriptor table to control the direct memory access of information with the buffer memory, the descriptor table comprising:

one or more direct memory access descriptor lists stored in the buffer memory, each of the one or more direct memory access descriptor lists including

a first pointer to point to a first starting address in the buffer memory from which to directly memory access data with the buffer memory,

type information regarding the type of data to be directly memory accessed with the buffer memory,

a second pointer to point to a second starting address in the buffer memory from which to directly memory access prior state information with the buffer memory,

a third pointer to point to a third starting address in the memory from which to directly memory access program code with the buffer memory.

10. The apparatus of claim 1, wherein each of the DMA controllers is a DMA master controller.

11. The apparatus of claim 1 wherein each functional model comprises a DMA controller coupled to the system bus via a bus arbitrator.

12. The apparatus of claim 1 wherein each functional unit comprises a core processor and the DMA controller is coupled between the core processor and the bus arbitrator;

and the system bus is coupled between each bus arbitrator and the buffer memory.

13. A method of distributed direct memory access to a global buffer memory, the method comprising:

providing a plurality of functional units each having a direct memory access controller and a processor coupled to the direct memory access controller;

requesting access to a system bus by at least one of the plurality of functional units to directly memory access the global buffer memory;

arbitrating access to the system bus by the at least one of the plurality of functional units using a plurality of bus arbitrators;

gaining access to the system bus by the at least one of the plurality of functional units;

establishing a direct memory access connection by the at least one of the plurality of functional units with the global buffer memory; and

reading data from or writing data into memory locations in the global buffer memory by the at least one of the plurality of functional units;

wherein each bus arbitrator is coupled between a direct memory access controller and the system bus to provide access to the system bus for the direct memory access controller.

14. The method of claim 13, further comprising

remapping a serial data stream into a parallel data stream prior to directly memory accessing the global buffer memory by the at least one of the plurality of functional units.

15. The method of claim 13, further comprising

remapping a parallel data stream into a serial data stream after directly memory accessing the global buffer memory by the at least one of the plurality of functional units.

16. The method of claim 13, wherein the steps are performed in a system on a chip.

17. The method of claim 16, wherein the system on a chip is a voice over packet system interfacing to a packet network on one end and a telephone network on an opposite end.

18. The method of claim 13, wherein each of the DMA controllers is a DMA master controller.

19. The method of claim 13 wherein requesting access comprises the functional unit requesting access through the DMA controller and to an arbitrator that provides the arbitrating.

20. The method of claim 13 further comprising providing voice over packet (VOP) on a single chip;

requesting access to the system bus by at least two of the plurality of functional units to direct memory access the global buffer memory;

arbitrating access to the system bus by the at least two of the plurality of functional units;

gaining access to the system bus by the at least two of the plurality of functional units;

establishing a direct memory access connection by the at least two of the plurality of functional units with the global buffer memory; and

reading data from or writing data into memory locations in the global buffer memory by the at least two of the plurality of functional units.

21. The method of claim 20 further comprising arbitrating access to the system bus to allow two microprocessors of two functional units to use two direct memory access controllers to access the global buffer memory.

22. The method of claim 13 further comprising communicating data between the functional units and the global buffer memory using the direct memory access connection;

and one of remapping serial data of the communicated data, compressing data of the communicated data on the fly, and decompressing data of the communicated data on the fly.

23. A distributed direct memory access control system comprising:

an integrated circuit chip having

a global memory; and

a plurality of direct memory access controllers distributed in functional blocks of a system on the integrated circuit chip and coupled to the global memory through a system bus, the plurality of direct memory access controllers to control direct memory access of the functional blocks of the system on the integrated circuit chip to the global memory, wherein each of the functional blocks include a processor coupled to the direct memory access controller;

a plurality of bus arbitrators, wherein each bus arbitrator is coupled between a direct memory access controller and the system bus to provide access to the system bus for the direct memory access controller.

24. The distributed direct memory access control system of claim 23, wherein the integrated circuit chip further has a system bus coupled between the global memory and the plurality of direct memory access controllers, the system bus including a data bus over which data can flow between the memory and the functional blocks of the system on the integrated circuit chip.

25. The distributed direct memory access control system of claim 24, wherein the system bus of the integrated circuit chip further includes DMA control lines to request direct memory access to the global memory and control the direct memory data flow with the global memory.

26. The distributed direct memory access control system of claim 23, wherein the global memory of the integrated circuit chip is a direct accessible memory and includes a direct memory access controller.

27. The distributed direct memory access control system of claim 26, wherein the direct memory access controller of the global memory includes

a receive first in first out (FIFO) buffer to store receive data,

a transmit first in first out (FIFO) buffer to store transmit data,

a data counter to count a number of data units that were transmitted to the memory and received from the memory by direct memory access, and

control logic coupled to the receive FIFO buffer, the transmit FIFO buffer, and the data counter to control the transmission and reception of data by direct memory access.

28. The distributed direct memory access control system of claim 23, wherein the plurality of direct memory access controllers of the integrated circuit chip include

a receive first in first out (FIFO) buffer to store receive data,

a transmit first in first out (FIFO) buffer to store transmit data,

a data counter to count a number of data units that were transmitted to the memory and received from the global memory by direct memory access, and

control logic coupled to the receive FIFO buffer, the transmit FIFO buffer, and the data counter to control the transmission and reception of data by direct memory access.

29. The distributed direct memory access control system of claim 28, wherein one of the plurality of direct memory access controllers of the integrated circuit chip further includes a remapper memory to remap parallel data into serial data and serial data into parallel data.

30. The distributed direct memory access control system of claim 23, wherein each of the plurality of direct memory access controllers is a master direct memory access controller.